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    DEVICE AND METHOD FOR UNIFORM STI RECESS
    91.
    发明申请
    DEVICE AND METHOD FOR UNIFORM STI RECESS 审中-公开
    用于均匀STI记录的装置和方法

    公开(公告)号：US20120032267A1

    公开(公告)日：2012-02-09

    申请号：US12851966

    申请日：2010-08-06

    申请人： KANGGUO CHENG ,  Bruce B. Doris ,  Ali Khakifirooz ,  Ghavam G. Shahidi

    发明人： KANGGUO CHENG ,  Bruce B. Doris ,  Ali Khakifirooz ,  Ghavam G. Shahidi

    IPC分类号： H01L29/06 ,  H01L21/302

    CPC分类号： H01L21/31111 ,  H01L21/31155 ,  H01L21/76237

    摘要： A semiconductor device and method for forming the semiconductor device include forming structures in a semiconductor substrate. The structures have two or more different spacings between them. A dielectric material is deposited in the spacings. Ion species are implanted to a depth in the dielectric material to change an etch rate of the dielectric material down to the depth. The dielectric material having the ion species is etched selective to the dielectric material below the depth such that a substantially uniform depth in the dielectric material is created across the at least two spacings.

    摘要翻译： 用于形成半导体器件的半导体器件和方法包括在半导体衬底中形成结构。 这些结构在它们之间具有两个或更多个不同的间隔。 电介质材料以间隔沉积。 将离子物质注入电介质材料中的深度以将介电材料的蚀刻速率改变到深度。 具有离子种类的电介质材料被选择性地蚀刻到深度以下的电介质材料，使得跨越至少两个间隔产生电介质材料中基本均匀的深度。

    Compressively Stressed FET Device Structures
    92.
    发明申请
    Compressively Stressed FET Device Structures 有权
    压缩式FET器件结构

    公开(公告)号：US20110303915A1

    公开(公告)日：2011-12-15

    申请号：US12813311

    申请日：2010-06-10

    申请人： Kangguo Cheng ,  Bruce B. Doris ,  Ali Khakifirooz ,  Pranita Kulkarni ,  Ghavam G. Shahidi

    发明人： Kangguo Cheng ,  Bruce B. Doris ,  Ali Khakifirooz ,  Pranita Kulkarni ,  Ghavam G. Shahidi

    IPC分类号： H01L27/088 ,  H01L21/8234

    CPC分类号： H01L21/823431 ,  H01L21/823412 ,  H01L21/823807 ,  H01L21/823821 ,  H01L29/66795 ,  H01L29/7843 ,  H01L29/7846 ,  H01L29/785

    摘要： Methods for fabricating FET device structures are disclosed. The methods include receiving a fin of a Si based material, and converting a region of the fin into an oxide element. The oxide element exerts pressure onto the fin where a Fin-FET device is fabricated. The exerted pressure induces compressive stress in the device channel of the Fin-FET device. The methods also include receiving a rectangular member of a Si based material and converting a region of the member into an oxide element. The methods further include patterning the member that N fins are formed in parallel, while being abutted by the oxide element, which exerts pressure onto the N fins. Fin-FET devices are fabricated in the compressed fins, which results in compressively stressed device channels. FET devices structures are also disclosed. An FET devices structure has a Fin-FET device with a fin of a Si based material. An oxide element is abutting the fin and exerts pressure onto the fin. The Fin-FET device channel is compressively stressed due to the pressure on the fin. A further FET device structure has Fin-FET devices in a row each having fins. An oxide element extending perpendicularly to the row of fins is abutting the fins and exerts pressure onto the fins. Device channels of the Fin-FET devices are compressively stressed due to the pressure on the fins.

    摘要翻译： 公开了用于制造FET器件结构的方法。 所述方法包括接收Si基材料的翅片，以及将鳍片的区域转换为氧化物元件。 氧化物元件在制造Fin-FET器件的鳍片上施加压力。 施加的压力在Fin-FET器件的器件沟道中引起压应力。 所述方法还包括接收Si基材料的矩形构件并将所述构件的区域转换为氧化物元件。 所述方法进一步包括在与N个翅片施加压力的同时被N型翅片平行地形成的构件图案化。 Fin-FET器件制造在压缩鳍片中，这导致压缩应力器件通道。 还公开了FET器件结构。 FET器件结构具有具有Si基材料的翅片的Fin-FET器件。 氧化物元件邻接翅片并对翅片施加压力。 Fin-FET器件通道由于鳍上的压力而受到压缩应力。 另外的FET器件结构具有各自具有鳍片的Fin-FET器件。 垂直于翅片排延伸的氧化物元件邻接散热片并对翅片施加压力。 Fin-FET器件的器件通道由于鳍片上的压力而受到压缩应力。

    HIGH-K/METAL GATE CMOS FINFET WITH IMPROVED PFET THRESHOLD VOLTAGE
    93.
    发明申请
    HIGH-K/METAL GATE CMOS FINFET WITH IMPROVED PFET THRESHOLD VOLTAGE 有权
    具有改进的PFET阈值电压的高K /金属栅极CMOS FINFET

    公开(公告)号：US20110108920A1

    公开(公告)日：2011-05-12

    申请号：US12614906

    申请日：2009-11-09

    申请人： VEERARAGHAVAN S. BASKER ,  Kangguo Cheng ,  Bruce B. Doris ,  Johnathan E. Faltermeier ,  Ali Khakifirooz

    发明人： VEERARAGHAVAN S. BASKER ,  Kangguo Cheng ,  Bruce B. Doris ,  Johnathan E. Faltermeier ,  Ali Khakifirooz

    IPC分类号： H01L29/49 ,  H01L21/84

    CPC分类号： H01L21/845 ,  H01L27/1211 ,  H01L29/1054 ,  H01L29/66795

    摘要： A device and method for fabrication of fin devices for an integrated circuit includes forming fin structures in a semiconductor material of a semiconductor device wherein the semiconductor material is exposed on sidewalls of the fin structures. A donor material is epitaxially deposited on the exposed sidewalls of the fin structures. A condensation process is applied to move the donor material through the sidewalls into the semiconductor material such that accommodation of the donor material causes a strain in the semiconductor material of the fin structures. The donor material is removed, and a field effect transistor is formed from the fin structure.

    摘要翻译： 用于制造用于集成电路的鳍片器件的器件和方法包括在半导体器件的半导体材料中形成鳍结构，其中半导体材料暴露在鳍结构的侧壁上。 施主材料外延地沉积在鳍结构的暴露的侧壁上。 施加冷凝过程以将供体材料通过侧壁移动到半导体材料中，使得供体材料的调节在翅片结构的半导体材料中引起应变。 施主材料被去除，并且从翅片结构形成场效应晶体管。

    FinFET device having reduce capacitance, access resistance, and contact resistance
    98.
    发明授权
    FinFET device having reduce capacitance, access resistance, and contact resistance 有权
    FinFET器件具有降低电容，访问电阻和接触电阻

    公开(公告)号：US08900936B2

    公开(公告)日：2014-12-02

    申请号：US13017966

    申请日：2011-01-31

    申请人： Pranita Kulkarni ,  Ali Khakifirooz ,  Kangguo Cheng ,  Bruce B. Doris ,  Ghavam Shahidi ,  Hemanth Jagannathan

    发明人： Pranita Kulkarni ,  Ali Khakifirooz ,  Kangguo Cheng ,  Bruce B. Doris ,  Ghavam Shahidi ,  Hemanth Jagannathan

    IPC分类号： H01L29/772 ,  H01L21/336 ,  H01L29/66 ,  H01L29/417 ,  H01L29/78

    CPC分类号： H01L29/66803 ,  H01L29/41791 ,  H01L29/785

    摘要： A fin field-effect transistor (finFET) device having reduced capacitance, access resistance, and contact resistance is formed. A buried oxide, a fin, a gate, and first spacers are provided. The fin is doped to form extension junctions extending under the gate. Second spacers are formed on top of the extension junctions. Each second spacer is adjacent to one of the first spacers to either side of the gate. The extension junctions and the buried oxide not protected by the gate, the first spacers, and the second spacers are etched back to create voids. The voids are filled with a semiconductor material such that a top surface of the semiconductor material extending below top surfaces of the extension junctions, to form recessed source-drain regions. A silicide layer is formed on the recessed source-drain regions, the extension junctions, and the gate not protected by the first spacers and the second spacers.

    摘要翻译： 形成具有减小的电容，存取电阻和接触电阻的鳍状场效应晶体管（finFET）器件。 提供掩埋氧化物，鳍状物，栅极和第一间隔物。 该鳍被掺杂以形成在栅极下方延伸的延伸结。 第二间隔件形成在延伸接头的顶部。 每个第二间隔件邻近门的任一侧的第一间隔件之一。 延伸结和未被栅极保护的埋入氧化物，第一间隔物和第二间隔物被回蚀刻以产生空隙。 空隙填充有半导体材料，使得半导体材料的顶表面延伸到延伸接头的顶表面之下，以形成凹陷的源极 - 漏极区域。 在凹陷的源极 - 漏极区域，延伸结点和不被第一间隔物和第二间隔物保护的栅极上形成硅化物层。

    FIN STRUCTURE FORMATION INCLUDING PARTIAL SPACER REMOVAL
    99.
    发明申请
    FIN STRUCTURE FORMATION INCLUDING PARTIAL SPACER REMOVAL 有权
    FIN结构形成，包括部分间隔开除

    公开(公告)号：US20140051247A1

    公开(公告)日：2014-02-20

    申请号：US13585395

    申请日：2012-08-14

    申请人： Kangguo Cheng ,  Bruce B. Doris ,  Ali Khakifirooz ,  Chun-Chen Yeh

    发明人： Kangguo Cheng ,  Bruce B. Doris ,  Ali Khakifirooz ,  Chun-Chen Yeh

    IPC分类号： H01L21/302

    CPC分类号： H01L21/32139 ,  H01L21/0337 ,  H01L21/3086 ,  H01L21/31144 ,  H01L29/66795

    摘要： A method of forming a semiconductor device includes forming a mandrel on top of a substrate; forming a first spacer adjacent to the mandrel on top of the substrate; forming a cut mask over the first spacer and the mandrel, such that the first spacer is partially exposed by the cut mask; partially removing the partially exposed first spacer; and etching the substrate to form a fin structure corresponding to the partially removed first spacer in the substrate.

    摘要翻译： 形成半导体器件的方法包括：在基底的顶部上形成心轴; 在所述基板的顶部上形成邻近所述心轴的第一间隔件; 在第一间隔件和心轴上形成切割掩模，使得第一间隔件被切割掩模部分地暴露; 部分地去除部分暴露的第一间隔件; 并且蚀刻所述衬底以形成对应于所述衬底中部分移除的第一间隔物的翅片结构。