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232 条记录 (耗时 0.083 秒)

    Statistical Design with Importance Sampling Reuse
    91.
    发明申请
    Statistical Design with Importance Sampling Reuse 审中-公开
    统计设计与重要性抽样重用

    公开(公告)号：US20120046929A1

    公开(公告)日：2012-02-23

    申请号：US12859871

    申请日：2010-08-20

    申请人： Rajiv V. Joshi ,  Rouwaida N. Kanj ,  Sani R. Nassif ,  Carl J. Radens

    发明人： Rajiv V. Joshi ,  Rouwaida N. Kanj ,  Sani R. Nassif ,  Carl J. Radens

    IPC分类号： G06F17/50

    CPC分类号： G06F11/076 ,  G06F11/008 ,  G06F11/079 ,  G06F17/5009 ,  G06F17/5022 ,  G06F2217/10

    摘要： A mechanism is provided for reusing importance sampling for efficient cell failure rate estimation of process variations and other design considerations. First, the mechanism performs a search across circuit parameters to determine failures with respect to a set of performance variables. For a single failure region, the initial search may be a uniform sampling of the parameter space. Mixture importance sampling (MIS) efficiently may estimate the single failure region. The mechanism then finds a center of gravity for each metric and finds importance samples. Then, for each new origin corresponding to a process variation or other design consideration, the mechanism finds a suitable projection and recomputes new importance sampling (IS) ratios.

    摘要翻译： 提供了一种用于重用采样的机制，用于有效地进行细胞故障率估计过程变化和其他设计考虑。 首先，该机制对电路参数进行搜索，以确定相对于一组性能变量的故障。 对于单个故障区域，初始搜索可以是参数空间的均匀采样。 混合重要性抽样（MIS）有效地估计单个故障区域。 然后，该机制找到每个度量的重心，并发现重要性样本。 然后，对于对应于过程变化或其他设计考虑的每个新的原点，机制找到合适的投影并重新计算新的重要性抽样（IS）比率。

    Anisotropic stress generation by stress-generating liners having a sublithographic width
    92.
    发明授权
    Anisotropic stress generation by stress-generating liners having a sublithographic width 有权
    具有亚光刻宽度的应力产生衬垫产生各向异性应力

    公开(公告)号：US07989291B2

    公开(公告)日：2011-08-02

    申请号：US12712369

    申请日：2010-02-25

    申请人： Lawrence A. Clevenger ,  Bruce B. Doris ,  Elbert E. Huang ,  Sampath Purushothaman ,  Carl J. Radens

    发明人： Lawrence A. Clevenger ,  Bruce B. Doris ,  Elbert E. Huang ,  Sampath Purushothaman ,  Carl J. Radens

    IPC分类号： H01L29/72

    CPC分类号： H01L21/31144 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/823871 ,  H01L21/84 ,  H01L27/1203 ,  H01L29/665 ,  H01L29/7833 ,  H01L29/7843

    摘要： A protruding structure having a linear edge is formed on a substrate. The protruding structure may be a gate line of a field effect transistor. A stress-generating liner is deposited on the substrate. A non-photosensitive self-assembling block copolymer layer containing at least two immiscible polymeric block components is deposited on the stress-generating liner, and is annealed to allow phase separation of immiscible components. The polymeric resist is developed to remove at least one of the at least two polymeric block components, which formed a pattern of nested lines due to the linear edge of the protruding structure. Linear nanoscale stripes are formed in the polymeric resist which is self-aligning and self-assembled. The stress-generating layer is patterned into linear stress-generating stripes having a sublithographic width. The linear stress-generating stripes provide a predominantly uniaxial stress along their lengthwise direction, providing an anisotropic stress to an underlying semiconductor device.

    摘要翻译： 在基板上形成具有线性边缘的突出结构。 突出结构可以是场效应晶体管的栅极线。 应力产生衬垫沉积在衬底上。 含有至少两种不混溶的聚合物嵌段组分的非感光性自组装嵌段共聚物层沉积在应力产生衬里上，并进行退火以允许不相容的组分相分离。 聚合物抗蚀剂被显影以除去至少两个聚合物嵌段组分中的至少一个，其由于突出结构的线性边缘而形成嵌套线的图案。 在自对准和自组装的聚合物抗蚀剂中形成线性纳米级条纹。 将应力产生层图案化成具有亚光刻宽度的线性应力产生条纹。 线性应力产生条纹沿其长度方向提供主要的单轴应力，向下面的半导体器件提供各向异性的应力。

    SRAM CELLS WITH ASYMMETRIC FLOATING-BODY PASS-GATE TRANSISTORS
    95.
    发明申请
    SRAM CELLS WITH ASYMMETRIC FLOATING-BODY PASS-GATE TRANSISTORS 审中-公开
    具有不对称浮动体态栅极晶体管的SRAM电池

    公开(公告)号：US20090073758A1

    公开(公告)日：2009-03-19

    申请号：US11857757

    申请日：2007-09-19

    申请人： Gregory G. Freeman ,  Qingqing Liang ,  Mario M. Pelella ,  Carl J. Radens ,  Huicai Zhong ,  Huilong Zhu

    发明人： Gregory G. Freeman ,  Qingqing Liang ,  Mario M. Pelella ,  Carl J. Radens ,  Huicai Zhong ,  Huilong Zhu

    IPC分类号： G11C11/34 ,  H01L21/00

    CPC分类号： G11C11/412

    摘要： The embodiments of the invention provide SRAM cells with asymmetric floating-body pass-gate transistors. More specifically, a semiconductor device includes an SRAM cell, a first pass-gate transistor, and a second pass-gate transistor. The first pass-gate transistor is connected to a first side of the SRAM cell, wherein the first pass-gate transistor comprises a first drain region and a first source region. The second pass-gate transistor is connected to a second side of the SRAM cell, wherein the second side is opposite the first side. The second pass-gate transistor comprises a second source region and a second drain region. Furthermore, the first source region and/or the second source region comprise a xenon implant. The first drain region and the second drain region each lack a xenon implant.

    摘要翻译： 本发明的实施例提供具有非对称浮体通过栅极晶体管的SRAM单元。 更具体地，半导体器件包括SRAM单元，第一通过栅极晶体管和第二通过栅极晶体管。 第一栅极晶体管连接到SRAM单元的第一侧，其中第一栅极晶体管包括第一漏极区域和第一源极区域。 第二通栅晶体管连接到SRAM单元的第二侧，其中第二侧与第一侧相对。 第二通栅晶体管包括第二源区和第二漏区。 此外，第一源区和/或第二源区包括氙植入物。 第一漏区和第二漏区各自缺少氙植入物。

    On-chip power supply regulator and temperature control system
    98.
    发明授权
    On-chip power supply regulator and temperature control system 失效
    片上电源调节器和温度控制系统

    公开(公告)号：US07214910B2

    公开(公告)日：2007-05-08

    申请号：US10884933

    申请日：2004-07-06

    申请人： Howard Hao Chen ,  William J. Ferrante ,  Louis L. Hsu ,  Carl J. Radens

    发明人： Howard Hao Chen ,  William J. Ferrante ,  Louis L. Hsu ,  Carl J. Radens

    IPC分类号： H05B1/02

    CPC分类号： G05D23/20 ,  G05D23/1931 ,  Y10T307/469

    摘要： An on-chip temperature control system includes a temperature sensor, which monitors a temperature of a chip, and a hysteresis comparator which checks whether the temperature is in an acceptable range. A reference adjustment circuit is responsive to the hysteresis comparator to adjust an on-chip voltage to control the temperature locally by adjusting a local supply voltage, if the temperature is out of range.

    摘要翻译： 片上温度控制系统包括监测芯片温度的温度传感器和检查温度是否在可接受范围内的滞后比较器。 如果温度超出范围，参考调节电路响应于迟滞比较器来调节片上电压以局部地调节局部电源电压来控制温度。

    Vertical MOSFET SRAM cell
    99.
    发明授权
    Vertical MOSFET SRAM cell 失效
    垂直MOSFET SRAM单元

    公开(公告)号：US07138685B2

    公开(公告)日：2006-11-21

    申请号：US10318495

    申请日：2002-12-11

    申请人： Louis L. Hsu ,  Oleg Gluschenkov ,  Jack A. Mandelman ,  Carl J. Radens

    发明人： Louis L. Hsu ,  Oleg Gluschenkov ,  Jack A. Mandelman ,  Carl J. Radens

    IPC分类号： H01L21/00

    CPC分类号： H01L27/11 ,  G11C11/412 ,  H01L21/84 ,  H01L27/1104 ,  H01L27/1203

    摘要： A method of forming an SRAM cell device includes the following steps. Form pass gate FET transistors and form a pair of vertical pull-down FET transistors with a first common body and a first common source in a silicon layer patterned into parallel islands formed on a planar insulator. Etch down through upper diffusions between cross-coupled inverter FET transistors to form pull-down isolation spaces bisecting the upper strata of pull-up and pull-down drain regions of the pair of vertical pull-down FET transistors, with the isolation spaces reaching down to the common body strata. Form a pair of vertical pull-up FET transistors with a second common body and a second common drain. Then, connect the FET transistors to form an SRAM cell.

    摘要翻译： 形成SRAM单元装置的方法包括以下步骤。 形成栅极FET晶体管并形成一对垂直下拉FET晶体管，其具有第一共同体和第一公共源，图案化为平坦绝缘体上形成平行岛的硅层。 通过交叉耦合的反相器FET晶体管之间的上扩散来蚀刻，以形成将一对垂直下拉FET晶体管的上拉和下拉漏极区的上层平分的下拉隔离空间，隔离空间达到 到共同的身体层。 形成一对具有第二共同体和第二公共漏极的垂直上拉FET晶体管。 然后，连接FET晶体管以形成SRAM单元。