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公开(公告)号：US20240257887A1
公开(公告)日：2024-08-01
申请号：US18630983
申请日：2024-04-09
发明人： Tawalin Opastrakoon , Renato C. Padilla , Vamsi Pavan Rayaprolu , Sampath K. Ratnam , Michael G. Miller , Gary F. Besinga , Christopher M. Smitchger
CPC分类号： G11C16/3468 , G11C16/10 , G11C16/26 , G11C16/3459
摘要： A configuration setting manager of a memory device receives a request to perform an adjustment operation on one or more configuration setting values of the memory device; calculate one or more updated configuration setting values by applying a multiplier value to the one or more configuration setting values based on a configuration adjustment definition associated with the one or more configuration setting values, wherein the multiplier value is associated with a number of memory operations performed on the memory device; and store the one or more updated configuration setting values to one or more corresponding configuration registers.
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公开(公告)号：US11984174B2
公开(公告)日：2024-05-14
申请号：US17249448
申请日：2021-03-02
发明人： Tawalin Opastrakoon , Renato C. Padilla , Vamsi Pavan Rayaprolu , Sampath K. Ratnam , Michael G. Miller , Gary F. Besinga , Christopher M. Smitchger
CPC分类号： G11C16/3468 , G11C16/10 , G11C16/26 , G11C16/3459
摘要： A configuration setting manager of a memory device receives a request to perform an adjustment operation on a set of configuration setting values for the memory device, where each configuration setting value of the set of configuration setting values is stored in a corresponding configuration register of a set of configuration registers; determines a configuration adjustment definition associated with one or more configuration setting values of the set of configuration setting values; calculates an updated set of configuration setting values by applying a multiplier value to the configuration adjustment definition, wherein the multiplier value is associated with a number of programming operations performed on the memory device; and stores the updated set of configuration setting values in the corresponding configuration registers.
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公开(公告)号：US11942160B2
公开(公告)日：2024-03-26
申请号：US18079843
申请日：2022-12-12
发明人： Kishore Kumar Muchherla , Harish R. Singidi , Vamsi Pavan Rayaprolu , Ashutosh Malshe , Sampath K. Ratnam
CPC分类号： G11C16/14 , G11C16/08 , G11C16/26 , G11C16/30 , G11C16/3404
摘要： A request to perform a secure erase operation for a memory component can be received. A voltage level of a pass voltage that is applied to unselected wordlines of the memory component during a read operation can be determined. A voltage pulse can be applied during a program operation to at least one wordline of the memory component to perform the secure erase operation. The voltage pulse can exceed the pass voltage applied to the unselected wordlines of the memory component during the read operation.
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公开(公告)号：US11853205B2
公开(公告)日：2023-12-26
申请号：US18172205
申请日：2023-02-21
发明人： Kishore Kumar Muchherla , Peter Feeley , Ashutosh Malshe , Daniel J. Hubbard , Christopher S. Hale , Kevin R. Brandt , Sampath K. Ratnam , Yun Li , Marc S. Hamilton
CPC分类号： G06F12/0253 , G06F3/064 , G06F3/0629 , G06F3/0634 , G06F3/0688 , G06F3/0689 , G06F12/00 , G06F12/0646 , G06F12/0891 , G06F2212/1044 , G06F2212/2022 , G06F2212/7205 , G11C11/5621 , G11C2211/5641
摘要： A memory system includes a memory array having a plurality of memory cells; and a controller coupled to the memory array, the controller configured to: designate a storage mode for a target set of memory cells based on valid data in a source block, wherein the target set of memory cells are configured with a capacity to store up to a maximum number of bits per cell, and the storage mode is for dynamically configuring the target set of memory cells in as cache memory that stores a number of bits less per cell than the corresponding maximum capacity.
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公开(公告)号：US11797441B2
公开(公告)日：2023-10-24
申请号：US17103419
申请日：2020-11-24
IPC分类号： G06F12/08 , G06F12/0802 , G06F12/02
CPC分类号： G06F12/0802 , G06F12/0253 , G06F2212/7205
摘要： An exempt portion of a data cache of a memory sub-system is identified. The exempt portion includes a first set of data blocks comprising first data written by a host system to the data cache. A collected portion of the data cache of the memory sub-system is identified. The collected portion includes a second set of data blocks comprising second data written by the host system. A media management operation is performed on the collected portion of the data cache to relocate the second data to a storage area of the memory sub-system that is at a higher data density than the data cache, wherein the exempt portion of the data cache is exempt from the media management operation.
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公开(公告)号：US20230325273A1
公开(公告)日：2023-10-12
申请号：US18207525
申请日：2023-06-08
发明人： Kishore Kumar Muchherla , Shane Nowell , Mustafa N. Kaynak , Sampath K. Ratnam , Peter Feeley , Sivagnanam Parthasarathy , Devin M. Batutis , Xiangang Luo
IPC分类号： G06F11/07
CPC分类号： G06F11/0793 , G06F11/0751 , G06F11/0727
摘要： Systems and methods are disclosed including a memory device and a processing device operatively coupled to the memory device. The processing device can perform operations including detecting a read error with respect to data residing in a first block of the memory device, wherein the first block is associated with a voltage offset bin; determining a most recently performed error-handling operation performed on a second block associated with the voltage offset bin; and performing the error-handling to recover the data.
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公开(公告)号：US11782847B2
公开(公告)日：2023-10-10
申请号：US17898138
申请日：2022-08-29
IPC分类号： G06F12/123 , G06F12/02 , G06F11/30
CPC分类号： G06F12/123 , G06F11/3037 , G06F12/0246 , G06F12/0253 , G06F2212/70 , G06F2212/7205 , G06F2212/7209
摘要： A first block that is assigned a first sequence identifier can be identified. A determination can be made as to whether the assigned first sequence identifier satisfies a threshold sequence identifier condition that corresponds to a difference between the first sequence identifier assigned to the first block and second sequence identifier assigned to a second block. In response to determining that the assigned first sequence identifier satisfies the threshold sequence identifier condition, a media management operation can be performed on the first block.
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公开(公告)号：US11748013B2
公开(公告)日：2023-09-05
申请号：US17949977
申请日：2022-09-21
发明人： Kishore Kumar Muchherla , Mustafa N. Kaynak , Jiangang Wu , Sampath K. Ratnam , Sivagnanam Parthasarathy , Peter Feeley , Karl D. Schuh
CPC分类号： G06F3/064 , G06F3/0625 , G06F3/0659 , G06F3/0673 , G11C16/10 , G11C16/0483
摘要： An initial value of a power cycle count associated with the memory device is identified. The power cycle count is incremented responsive to detecting a powering up of the memory device. Responsive to programming a block residing in the memory device, the block is associated with a current block family associated with the memory device. A currently value of the power cycle count is determined. Responsive to determining that a difference between the initial value of the power cycle count and the current value of the power cycle count satisfies a predefined condition, the current block family is closed.
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公开(公告)号：US11726874B2
公开(公告)日：2023-08-15
申请号：US17249399
申请日：2021-03-01
发明人： Vamsi Rayaprolu , Sivagnanam Parthasarathy , Sampath K. Ratnam , Peter Feeley , Kishore Kumar Muchherla
CPC分类号： G06F11/1076 , G06F3/064 , G06F3/0619 , G06F3/0673 , G06F11/1004 , G06F11/1012
摘要： A request to retrieve user data stored at a memory device is received and a first error control operation associated with the user data is performed. An indication of a failure of the first error control operation is received, and in response, a subset of system data stored at the memory device is identified. A second error control operation is performed on the subset of the system data to retrieve the subset of the system data stored at the memory device, and the user data is read by using the subset of the system data retrieved based on the performing of the second error control operation.
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100.发明授权公开(公告)号：US11676664B2
公开(公告)日：2023-06-13
申请号：US17883538
申请日：2022-08-08
发明人： Kishore Kumar Muchherla , Sampath K. Ratnam , Shane Nowell , Sivagnanam Parthasarathy , Mustafa N. Kaynak , Karl D. Schuh , Peter Feeley , Jiangang Wu
CPC分类号： G11C16/102 , G11C16/20 , G11C16/26 , G11C16/30 , G11C16/32 , G11C16/3495
摘要： A processing device of a memory sub-system is configured to detect a power on event that is associated with a memory device and indicates that power has been restored to the memory device; estimate a duration of a power off state preceding the power on event associated with the memory device; and update voltage bin assignments of a plurality of blocks associated with the memory device based on the duration of the power off state.
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