公开(公告)号：US20160284739A1

公开(公告)日：2016-09-29

申请号：US15180642

申请日：2016-06-13

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Hideomi SUZAWA ,  Shinya SASAGAWA ,  Taiga MURAOKA

IPC: H01L27/12 ,  H01L29/786 ,  H01L21/465 ,  H01L29/66

CPC classification number: H01L27/127 ,  G02F1/134309 ,  G02F1/136227 ,  G02F1/167 ,  G09F21/04 ,  G09G3/3648 ,  G09G3/3677 ,  G09G2300/0408 ,  G09G2300/0809 ,  G09G2310/0251 ,  G09G2310/0286 ,  G09G2310/08 ,  G11C19/28 ,  H01L21/465 ,  H01L27/1225 ,  H01L27/124 ,  H01L27/3262 ,  H01L29/66969 ,  H01L29/7869 ,  H01L29/78696

Abstract: An object is to establish a processing technique in manufacture of a semiconductor device in which an oxide semiconductor is used. A gate electrode is formed over a substrate, a gate insulating layer is formed over the gate electrode, an oxide semiconductor layer is formed over the gate insulating layer, the oxide semiconductor layer is processed by wet etching to form an island-shaped oxide semiconductor layer, a conductive layer is formed to cover the island-shaped oxide semiconductor layer, the conductive layer is processed by dry etching to form a source electrode, and a drain electrode and part of the island-shaped oxide semiconductor layer is removed by dry etching to form a recessed portion in the island-shaped oxide semiconductor layer.

公开(公告)号：US20160172501A1

公开(公告)日：2016-06-16

申请号：US15049554

申请日：2016-02-22

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Shunpei YAMAZAKI ,  Masayuki SAKAKURA ,  Hideomi SUZAWA

IPC: H01L29/786 ,  H01L29/04

CPC classification number: H01L29/78696 ,  H01L27/1052 ,  H01L27/1225 ,  H01L27/14616 ,  H01L29/04 ,  H01L29/045 ,  H01L29/24 ,  H01L29/66969 ,  H01L29/7854 ,  H01L29/7869 ,  H01L29/78693

Abstract: A semiconductor device having a structure which can prevent a decrease in electrical characteristics due to miniaturization is provided. The semiconductor device includes, over an insulating surface, a stack in which a first oxide semiconductor layer and a second oxide semiconductor layer are sequentially formed, and a third oxide semiconductor layer covering part of a surface of the stack. The third oxide semiconductor layer includes a first layer in contact with the stack and a second layer over the first layer. The first layer includes a microcrystalline layer, and the second layer includes a crystalline layer in which c-axes are aligned in a direction perpendicular a surface of the first layer.

Abstract translation: 提供具有能够防止由于小型化引起的电特性降低的结构的半导体器件。 半导体器件在绝缘表面上包括其中顺序形成第一氧化物半导体层和第二氧化物半导体层的堆叠，以及覆盖堆叠表面的一部分的第三氧化物半导体层。 第三氧化物半导体层包括与堆叠接触的第一层和在第一层上的第二层。 第一层包括微晶层，第二层包括其中c轴在垂直于第一层的表面的方向上排列的结晶层。

公开(公告)号：US20160163839A1

公开(公告)日：2016-06-09

申请号：US15044422

申请日：2016-02-16

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Shunpei YAMAZAKI ,  Hideomi SUZAWA

IPC: H01L29/66 ,  H01L21/477 ,  H01L21/02 ,  H01L29/24 ,  H01L29/786 ,  H01L21/467

CPC classification number: H01L29/66969 ,  H01L21/02554 ,  H01L21/02565 ,  H01L21/0262 ,  H01L21/02631 ,  H01L21/467 ,  H01L21/477 ,  H01L29/247 ,  H01L29/263 ,  H01L29/78693 ,  H01L29/78696

Abstract: A semiconductor device formed using an oxide semiconductor layer and having small electrical characteristic variation is provided. A highly reliable semiconductor device including an oxide semiconductor layer and exhibiting stable electric characteristics is provided. Further, a method for manufacturing the semiconductor device is provided. In the semiconductor device, an oxide semiconductor layer is used for a channel formation region, a multilayer film which includes an oxide layer in which the oxide semiconductor layer is wrapped is provided, and an edge of the multilayer film has a curvature in a cross section.

Abstract translation: 提供了使用氧化物半导体层形成且具有小的电特性变化的半导体器件。 提供了包括氧化物半导体层并且表现出稳定的电特性的高度可靠的半导体器件。 此外，提供了一种用于制造半导体器件的方法。 在半导体装置中，使用氧化物半导体层作为沟道形成区域，设置包含氧化物半导体层被包覆的氧化物层的多层膜，多层膜的边缘在截面上具有曲率 。

公开(公告)号：US20160087107A1

公开(公告)日：2016-03-24

申请号：US14954155

申请日：2015-11-30

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Shunpei YAMAZAKI ,  Hideomi SUZAWA ,  Yutaka OKAZAKI ,  Hidekazu MIYAIRI

IPC: H01L29/786

CPC classification number: H01L29/78606 ,  H01L21/8221 ,  H01L27/0688 ,  H01L29/42384 ,  H01L29/78603 ,  H01L29/7869 ,  H01L29/78696

Abstract: A structure is employed in which a first protective insulating layer; an oxide semiconductor layer over the first protective insulating layer; a source electrode and a drain electrode that are electrically connected to the oxide semiconductor layer; a gate insulating layer that is over the source electrode and the drain electrode and overlaps with the oxide semiconductor layer; a gate electrode that overlaps with the oxide semiconductor layer with the gate insulating layer provided therebetween; and a second protective insulating layer that covers the source electrode, the drain electrode, and the gate electrode are included. Furthermore, the first protective insulating layer and the second protective insulating layer each include an aluminum oxide film that includes an oxygen-excess region, and are in contact with each other in a region where the source electrode, the drain electrode, and the gate electrode are not provided.

Abstract translation: 采用其中第一保护绝缘层的结构; 在所述第一保护绝缘层上的氧化物半导体层; 与氧化物半导体层电连接的源电极和漏电极; 栅极绝缘层，位于源电极和漏电极之上并与氧化物半导体层重叠; 与所述氧化物半导体层重叠的栅电极，其间设置有所述栅极绝缘层; 并且包括覆盖源电极，漏电极和栅电极的第二保护绝缘层。 此外，第一保护绝缘层和第二保护绝缘层各自包括氧化物膜，该氧化铝膜包括氧过剩区域，并且在源电极，漏电极和栅电极的区域中彼此接触 没有提供

公开(公告)号：US20160049521A1

公开(公告)日：2016-02-18

申请号：US14926737

申请日：2015-10-29

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Sachiaki TEZUKA ,  Hideomi SUZAWA ,  Akihisa SHIMOMURA ,  Tetsuhiro TANAKA

IPC: H01L29/786 ,  H01L21/02 ,  H01L29/66

CPC classification number: H01L29/7869 ,  H01L21/02318 ,  H01L21/02323 ,  H01L21/0234 ,  H01L29/247 ,  H01L29/66969 ,  H01L29/78693

Abstract: A highly reliable semiconductor device including an oxide semiconductor is provided. Oxygen is supplied from a base insulating layer provided below an oxide semiconductor layer to a channel formation region, whereby oxygen vacancies which might be generated in the channel formation region are filled. Further, a protective insulating layer containing a small amount of hydrogen and functioning as a barrier layer having a low permeability to oxygen is formed over the gate electrode layer so as to cover side surfaces of an oxide layer and a gate insulating layer that are provided over the oxide semiconductor layer, whereby release of oxygen from the gate insulating layer and/or the oxide layer is prevented and generation of oxygen vacancies in a channel formation region is prevented.

Abstract translation: 提供了包括氧化物半导体的高度可靠的半导体器件。 氧气从设置在氧化物半导体层下方的基底绝缘层供给到沟道形成区域，由此填充可能在沟道形成区域中产生的氧空位。 此外，在栅电极层上形成包含少量氢并用作具有低氧渗透性的阻挡层的保护绝缘层，以覆盖设置在氧化物层和栅绝缘层上的侧表面 氧化物半导体层，从而防止了从栅极绝缘层和/或氧化物层的氧的释放，并且防止了沟道形成区域中的氧空位的产生。

公开(公告)号：US20150270288A1

公开(公告)日：2015-09-24

申请号：US14659656

申请日：2015-03-17

Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.

Inventor： Shunpei YAMAZAKI ,  Hideomi SUZAWA

IPC: H01L27/12 ,  H01L29/16 ,  H01L29/786 ,  H01L29/06 ,  H01L49/02 ,  H01L29/78 ,  H01L27/06 ,  H01L29/24

CPC classification number: H01L29/7869 ,  H01L27/0629 ,  H01L27/0688 ,  H01L27/1156 ,  H01L27/1225 ,  H01L29/0657 ,  H01L29/16 ,  H01L29/24 ,  H01L29/78

Abstract: Provided is a highly integrated semiconductor device, a semiconductor device with large storage capacity with respect to an area occupied by a capacitor, a semiconductor device capable of high-speed writing, a semiconductor device capable of high-speed reading, a semiconductor device with low power consumption, or a highly reliable semiconductor device. The semiconductor device includes a first transistor, a second transistor, and a capacitor. A conductor penetrates and connects the first transistor, the capacitor, and the second transistor. An insulator is provided on a side surface of the conductor that penetrates the capacitor.

Abstract translation: 提供了一种高度集成的半导体器件，相对于电容器占据的面积具有大的存储容量的半导体器件，能够高速写入的半导体器件，能够高速读取的半导体器件，具有低速读取的半导体器件 功耗或高度可靠的半导体器件。 半导体器件包括第一晶体管，第二晶体管和电容器。 导体穿透并连接第一晶体管，电容器和第二晶体管。 在穿过电容器的导体的侧表面上提供绝缘体。

公开(公告)号：US20150069385A1

公开(公告)日：2015-03-12

申请号：US14476767

申请日：2014-09-04

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Yoshitaka YAMAMOTO ,  Tetsuhiro TANAKA ,  Takayuki INOUE ,  Hideomi SUZAWA

IPC: H01L29/786 ,  H01L29/66 ,  H01L27/115 ,  H01L29/792

CPC classification number: H01L29/7869 ,  G11C7/04 ,  G11C11/24 ,  G11C14/0054 ,  G11C16/0466 ,  G11C16/3404 ,  H01L27/1225 ,  H01L29/42384 ,  H01L29/4908 ,  H01L29/66969 ,  H01L29/78648 ,  H01L29/78696 ,  H01L29/7881

Abstract: A method for adjusting threshold of a semiconductor device is provided. In a plurality of semiconductor devices each including a semiconductor, a source or drain electrode electrically in contact with the semiconductor, a gate electrode, and a charge trap layer between a gate electrode and the semiconductor, a state where the potential of the gate electrode is set higher than the potential of the source or drain electrode while the semiconductor devices are heated at 150° C. or higher and 300° C. or lower is kept for one second or longer to trap electrons in the charge trap layer, so that the threshold is increased and Icut is reduced. Here, the potential difference between the gate electrode and the source or drain electrode is set so that it is different between the semiconductor devices, and the thresholds of the semiconductor devices are adjusted to be appropriate to each purpose.

Abstract translation: 提供了一种用于调整半导体器件的阈值的方法。 在多个半导体器件中，每个半导体器件包括半导体，与半导体电接触的源极或漏极，栅电极和栅电极与半导体之间的电荷陷阱层，栅电极的电位为 设定为高于源极或漏极的电位，同时将半导体器件在150℃以上且300℃以下的温度加热保持1秒以上以在电荷陷阱层中捕获电子，使得 阈值增加并且Icut减小。 这里，栅电极和源电极或漏电极之间的电位差被设定为在半导体器件之间不同，并且将半导体器件的阈值调整为适合于每个目的。

公开(公告)号：US20140179058A1

公开(公告)日：2014-06-26

申请号：US14191853

申请日：2014-02-27

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Hideomi SUZAWA ,  Shinya SASAGAWA ,  Taiga MURAOKA ,  Shunichi ITO ,  Miyuki HOSOBA

IPC: H01L29/66

CPC classification number: H01L29/66969 ,  H01L27/1225 ,  H01L27/1288 ,  H01L29/66742 ,  H01L29/78621 ,  H01L29/7869

Abstract: An object is to manufacture a semiconductor device including an oxide semiconductor at low cost with high productivity in such a manner that a photolithography process is simplified by reducing the number of light-exposure masks In a method for manufacturing a semiconductor device including a channel-etched inverted-staggered thin film transistor, an oxide semiconductor film and a conductive film are etched using a mask layer formed with the use of a multi-tone mask which is a light-exposure mask through which light is transmitted so as to have a plurality of intensities. In etching steps, a first etching step is performed by wet etching in which an etchant is used, and a second etching step is performed by dry etching in which an etching gas is used.

Abstract translation: 本发明的目的是以低成本，高生产率制造包括氧化物半导体的半导体器件，使得通过减少曝光掩模的数量来简化光刻工艺。在包括通道蚀刻的半导体器件的制造方法中 倒置交错薄膜晶体管，氧化物半导体膜和导电膜使用掩模层进行蚀刻，该掩模层使用作为透光的多色调掩模形成，该透光掩模通过该曝光掩模透射，以便具有多个 强度 在蚀刻步骤中，通过使用蚀刻剂的湿式蚀刻进行第一蚀刻步骤，并且通过使用蚀刻气体的干法蚀刻进行第二蚀刻步骤。

公开(公告)号：US20140103339A1

公开(公告)日：2014-04-17

申请号：US14054110

申请日：2013-10-15

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Shunpei YAMAZAKI ,  Hideomi SUZAWA

IPC: H01L29/786 ,  H01L29/66 ,  H01L29/26

CPC classification number: H01L29/66969 ,  H01L21/02554 ,  H01L21/02565 ,  H01L21/0262 ,  H01L21/02631 ,  H01L21/467 ,  H01L21/477 ,  H01L29/247 ,  H01L29/263 ,  H01L29/78693 ,  H01L29/78696

Abstract: A semiconductor device formed using an oxide semiconductor layer and having small electrical characteristic variation is provided. A highly reliable semiconductor device including an oxide semiconductor layer and exhibiting stable electric characteristics is provided. Further, a method for manufacturing the semiconductor device is provided. In the semiconductor device, an oxide semiconductor layer is used for a channel formation region, a multilayer film which includes an oxide layer in which the oxide semiconductor layer is wrapped is provided, and an edge of the multilayer film has a curvature in a cross section.

Abstract translation: 提供了使用氧化物半导体层形成且具有小的电特性变化的半导体器件。 提供了包括氧化物半导体层并且表现出稳定的电特性的高度可靠的半导体器件。 此外，提供了一种用于制造半导体器件的方法。 在半导体装置中，使用氧化物半导体层作为沟道形成区域，设置包含氧化物半导体层被包覆的氧化物层的多层膜，多层膜的边缘在截面上具有曲率 。

公开(公告)号：US20140103337A1

公开(公告)日：2014-04-17

申请号：US14054078

申请日：2013-10-15

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Shunpei YAMAZAKI ,  Hideomi SUZAWA ,  Shinya SASAGAWA ,  Tetsuhiro TANAKA

IPC: H01L21/02 ,  H01L29/26 ,  H01L29/78

CPC classification number: H01L21/02565 ,  H01L21/02617 ,  H01L21/02631 ,  H01L27/1156 ,  H01L29/26 ,  H01L29/66969 ,  H01L29/78 ,  H01L29/7869 ,  H01L29/78693 ,  H01L29/78696

Abstract: To provide a highly reliable semiconductor device including an oxide semiconductor by suppression of change in its electrical characteristics. Oxygen is supplied from a base insulating layer provided below an oxide semiconductor layer and a gate insulating layer provided over the oxide semiconductor layer to a region where a channel is formed, whereby oxygen vacancies which might be generated in the channel are filled. Further, extraction of oxygen from the oxide semiconductor layer by a source electrode layer or a drain electrode layer in the vicinity of the channel formed in the oxide semiconductor layer is suppressed, whereby oxygen vacancies which might be generated in a channel are suppressed.

Abstract translation: 通过抑制其电特性的变化来提供包括氧化物半导体的高度可靠的半导体器件。 氧气由设置在氧化物半导体层下方的基底绝缘层和设置在氧化物半导体层上的栅极绝缘层提供到形成沟道的区域，从而填充可能在沟道中产生的氧空位。 此外，通过在氧化物半导体层中形成的沟道附近的源极电极层或漏极电极层从氧化物半导体层提取氧被抑制，由此抑制在沟道中可能产生的氧空位。