公开(公告)号：US12255156B2

公开(公告)日：2025-03-18

申请号：US18336303

申请日：2023-06-16

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chien Hung Chen ,  Shu-Shen Yeh ,  Po-Chen Lai ,  Po-Yao Lin ,  Shin-Puu Jeng

IPC: H01L23/16 ,  H01L21/48 ,  H01L21/56 ,  H01L23/00 ,  H01L23/31 ,  H01L23/58

Abstract: A semiconductor package and a method of forming the same are provided. The semiconductor package includes a package substrate and a semiconductor device mounted on the surface of the package substrate. A first ring is disposed over the surface of the package substrate and surrounds the semiconductor device. A second ring is disposed over the top surface of the first ring. Also, a protruding part and a matching recessed part are formed on the top surface of the first ring and the bottom surface of the second ring, respectively. The protruding part extends into and engages with the recessed part to connect the first ring and the second ring. An adhesive layer is disposed between the surface of the package substrate and the bottom surface of the first ring for attaching the first ring and the overlying second ring to the package substrate.

公开(公告)号：US12255078B2

公开(公告)日：2025-03-18

申请号：US18447443

申请日：2023-08-10

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Po-Chen Lai ,  Ming-Chih Yew ,  Po-Yao Lin ,  Chien-Sheng Chen ,  Shin-Puu Jeng

IPC: H01L21/00 ,  H01L21/56 ,  H01L23/31

Abstract: Semiconductor devices and methods of manufactured are presented in which a first redistribution structure is formed, semiconductor devices are bonded to the first redistribution structure, and the semiconductor devices are encapsulated in an encapsulant. First openings are formed within the encapsulant, such as along corners of the encapsulant, in order to help relieve stress and reduce cracks.

公开(公告)号：US20250079428A1

公开(公告)日：2025-03-06

申请号：US18948727

申请日：2024-11-15

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Yi-Wen Wu ,  Po-Yao Chuang ,  Meng-Liang Lin ,  Techi Wong ,  Shih-Ting Hung ,  Po-Hao Tsai ,  Shin-Puu Jeng

IPC: H01L25/00 ,  H01L21/56 ,  H01L23/00 ,  H01L25/18

Abstract: Packaged devices and methods of manufacturing the devices are described herein. The packaged devices may be fabricated using heterogeneous devices and asymmetric dual-side molding on a multi-layered redistribution layer (RDL) structure. The packaged devices may be formed with a heterogeneous three-dimensional (3D) Fan-Out System-in-Package (SiP) structure having small profiles and can be formed using a single carrier substrate.

公开(公告)号：US20240387378A1

公开(公告)日：2024-11-21

申请号：US18787615

申请日：2024-07-29

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Shin-Puu Jeng ,  Po-Yao Chuang ,  Shuo-Mao Chen ,  Feng-Cheng Hsu

IPC: H01L23/532 ,  H01L21/56 ,  H01L21/768 ,  H01L23/00 ,  H01L23/31 ,  H01L23/522

Abstract: Semiconductor devices and methods of manufacture are provided wherein multiple integrated passive devices are integrated together utilizing an integrated fan out process in order to form a larger device with a smaller footprint. In particular embodiments the multiple integrated passive devices are capacitors which, once stacked together, can be utilized to provide a larger overall capacitance than any single passive device can obtain with a similar footprint.

公开(公告)号：US20240387339A1

公开(公告)日：2024-11-21

申请号：US18787212

申请日：2024-07-29

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Shu-Shen Yeh ,  Che-Chia Yang ,  Chin-Hua Wang ,  Chia-Kuei Hsu ,  Po-Yao Lin ,  Shin-Puu Jeng

IPC: H01L23/498 ,  H01L21/48 ,  H01L23/00

Abstract: A package structure and a method of forming the same are provided. The package structure includes an integrated circuit die and a redistribution structure bonded to the integrated circuit die. The redistribution structure includes a first insulating layer, a second insulating layer interposed between the first insulating layer and the integrated circuit die, and a first metallization pattern in the first insulating layer and the second insulating layer. The first metallization pattern includes a first conductive line and a first conductive via coupled to the first conductive line. The first conductive line is in the second insulating layer. The first conductive via is in the first insulating layer. The first conductive line includes a first conductive pad coupled to the first conductive via, a second conductive pad, and a curved portion connecting the first conductive pad to the second conductive pad.

公开(公告)号：US20240379494A1

公开(公告)日：2024-11-14

申请号：US18784233

申请日：2024-07-25

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Yu Chen Lee ,  Shu-Shen Yeh ,  Chia-Kuei Hsu ,  Po-Yao Lin ,  Shin-Puu Jeng

IPC: H01L23/373 ,  H01L23/00 ,  H01L23/31 ,  H01L23/367 ,  H01L23/498 ,  H01L25/065

Abstract: A semiconductor structure includes: a substrate; a package attached to a first surface of the substrate, where the package includes: an interposer, where a first side of the interposer is bonded to the first surface of the substrate through first conductive bumps; dies attached to a second side of the interposer opposing the first side; and a molding material on the second side of the interposer around the dies; a plurality of thermal interface material (TIM) films on a first surface of the package distal from the substrate, where each of the TIM films is disposed directly over at least one respective die of the dies; and a heat-dissipation lid attached to the first surface of the substrate, where the package and the plurality of TIM films are disposed in an enclosed space between the heat-dissipation lid and the substrate, where the heat-dissipation lid contacts the plurality of TIM films.

公开(公告)号：US20240371843A1

公开(公告)日：2024-11-07

申请号：US18775285

申请日：2024-07-17

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Shin-Puu Jeng ,  Shuo-Mao Chen ,  Feng-Cheng Hsu

IPC: H01L25/16 ,  H01L21/48 ,  H01L21/56 ,  H01L23/00 ,  H01L23/31 ,  H01L23/538 ,  H01L25/00 ,  H01L25/065

Abstract: A method includes bonding a first package component and a second package component to an interposer. The first package component includes a core device die, and the second package component includes a memory die. An Independent Passive Device (IPD) die is bonded directly to the interposer. The IPD die is electrically connected to the first package component through a first conductive path in the interposer. A package substrate is bonded to the interposer die. The package substrate is on an opposing side of the interposer than the first package component and the second package component.

公开(公告)号：US12113025B2

公开(公告)日：2024-10-08

申请号：US17881981

申请日：2022-08-05

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Shin-Puu Jeng ,  Shuo-Mao Chen ,  Hsien-Wen Liu ,  Po-Yao Chuang ,  Feng-Cheng Hsu ,  Po-Yao Lin

IPC: H01L23/538 ,  H01L21/768 ,  H01L23/00 ,  H01L23/31 ,  H01L23/498 ,  H01L25/00 ,  H01L25/10 ,  H01L21/48 ,  H01L25/065

CPC classification number: H01L23/5385 ,  H01L21/76885 ,  H01L23/3128 ,  H01L23/49811 ,  H01L23/49827 ,  H01L23/49833 ,  H01L23/5389 ,  H01L24/16 ,  H01L24/19 ,  H01L24/20 ,  H01L24/32 ,  H01L24/73 ,  H01L24/81 ,  H01L24/83 ,  H01L24/92 ,  H01L24/95 ,  H01L25/105 ,  H01L25/50 ,  H01L21/486 ,  H01L23/49816 ,  H01L23/5384 ,  H01L25/0655 ,  H01L25/0657 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/19 ,  H01L2224/211 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/73204 ,  H01L2224/73265 ,  H01L2224/81801 ,  H01L2224/83104 ,  H01L2224/83855 ,  H01L2224/92125 ,  H01L2224/95 ,  H01L2225/0651 ,  H01L2225/1035 ,  H01L2225/1041 ,  H01L2225/1058 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2224/48091 ,  H01L2924/00014 ,  H01L2924/181 ,  H01L2924/00012 ,  H01L2224/73204 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2924/00

Abstract: A method includes forming a redistribution structure over a carrier, the redistribution structure having conductive features on a surface of the redistribution structure distal the carrier; forming a conductive pillar over the surface of the redistribution structure; attaching a die to the surface of the redistribution structure adjacent to the conductive pillar, where die connectors of the die are electrically coupled to the conductive features of the redistribution structure; and attaching a pre-made substrate to the conductive pillar through a conductive joint, where the conductive joint is on the conductive pillar and comprises a different material from the conductive pillar, where the conductive joint and the conductive pillar electrically couple the redistribution structure to the pre-made substrate.

公开(公告)号：US20240249994A1

公开(公告)日：2024-07-25

申请号：US18624903

申请日：2024-04-02

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Shu-Shen Yeh ,  Chin-Hua Wang ,  Chia-Kuei Hsu ,  Po-Yao Lin ,  Shin-Puu Jeng

IPC: H01L23/367 ,  H01L21/48 ,  H01L21/56 ,  H01L23/00 ,  H01L23/31 ,  H01L23/498 ,  H01L25/00 ,  H01L25/065

CPC classification number: H01L23/3675 ,  H01L21/4853 ,  H01L21/4857 ,  H01L21/4871 ,  H01L21/563 ,  H01L21/565 ,  H01L23/3128 ,  H01L23/3135 ,  H01L23/49822 ,  H01L24/16 ,  H01L25/0655 ,  H01L25/50 ,  H01L2224/16227

Abstract: Semiconductor devices and methods of manufacture which utilize lids in order to constrain thermal expansion during annealing are presented. In some embodiments lids are placed and attached on encapsulant and, in some embodiments, over first semiconductor dies. As such, when heat is applied, and the encapsulant attempts to expand, the lid will work to constrain the expansion, reducing the amount of stress that would otherwise accumulate within the encapsulant.

公开(公告)号：US20240222218A1

公开(公告)日：2024-07-04

申请号：US18604957

申请日：2024-03-14

Applicant: Taiwan Semiconductor Manufacturing Co, Ltd.

Inventor： Wensen Hung ,  Szu-Po Huang ,  Hsiang-Fan Lee ,  Kim Hong Chen ,  Chi-Hsi Wu ,  Shin-Puu Jeng

IPC: H01L23/36 ,  H01L23/00 ,  H01L23/04 ,  H01L23/10 ,  H01L23/367 ,  H01L23/42 ,  H01L23/498 ,  H01L25/065 ,  H01L25/18

CPC classification number: H01L23/36 ,  H01L23/04 ,  H01L23/10 ,  H01L23/3675 ,  H01L23/3677 ,  H01L23/42 ,  H01L23/49822 ,  H01L23/49827 ,  H01L25/0652 ,  H01L25/0657 ,  H01L23/49816 ,  H01L24/13 ,  H01L24/16 ,  H01L24/32 ,  H01L24/73 ,  H01L24/83 ,  H01L24/92 ,  H01L25/18 ,  H01L2224/13025 ,  H01L2224/131 ,  H01L2224/16145 ,  H01L2224/16227 ,  H01L2224/29011 ,  H01L2224/291 ,  H01L2224/2919 ,  H01L2224/29294 ,  H01L2224/29339 ,  H01L2224/32225 ,  H01L2224/32245 ,  H01L2224/33181 ,  H01L2224/33519 ,  H01L2224/73204 ,  H01L2224/73253 ,  H01L2224/81815 ,  H01L2224/83191 ,  H01L2224/92125 ,  H01L2224/92225 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06541 ,  H01L2225/06568 ,  H01L2225/06589 ,  H01L2924/1431 ,  H01L2924/1432 ,  H01L2924/1434 ,  H01L2924/1436 ,  H01L2924/15311 ,  H01L2924/16153 ,  H01L2924/16251 ,  H01L2924/1679 ,  H01L2924/181 ,  H01L2924/19041 ,  H01L2924/19042 ,  H01L2924/19043 ,  H01L2924/19105

Abstract: A package includes a substrate having a conductive layer, and the conductive layer comprises an exposed portion. A die stack is disposed over the substrate and electrically connected to the conductive layer. A high thermal conductivity material is disposed over the substrate and contacting the exposed portion of the conductive layer. The package further includes a contour ring over and contacting the high thermal conductivity material.