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公开(公告)号：US20070211547A1
公开(公告)日：2007-09-13
申请号：US11797984
申请日：2007-05-09
IPC分类号： G11C7/06
CPC分类号： G11C7/065 , G11C5/025 , G11C5/14 , G11C7/06 , G11C7/08 , G11C11/406 , G11C11/4074 , G11C11/4091 , G11C2207/065 , H01L27/0207 , H01L27/10894
摘要： A sense amplifier capable of performing high-speed data sense operation with lower power consumption using a minuscule signal from a memory cell even in a case where a memory array voltage is reduced. A plurality of drive switches for over-driving are distributively arranged in a sense amplifier area, and a plurality of drive switches for restore operation are concentratively disposed at one end of a row of the sense amplifiers. A potential for over-driving is supplied using a meshed power line circuit. Through the use of the drive switches for over-driving, initial sense operation can be performed on data line pairs with a voltage having an amplitude larger than a data-line amplitude, allowing implementation of high-speed sense operation. The distributed arrangement of the drive switched for over-driving makes it possible to dispersively supply current in sense operation, thereby reducing a difference in sense voltage with respect to far and near positions of the sense amplifiers.
摘要翻译： 一种读出放大器即使在存储器阵列电压降低的情况下，也能够使用来自存储单元的微小信号，以较低的功耗进行高速数据检测操作。 用于过驱动的多个驱动开关被分布地布置在感测放大器区域中，并且用于恢复操作的多个驱动开关被集中地布置在一行的读出放大器的一端。 使用网状电力线电路提供过驱动的可能性。 通过使用用于过驱动的驱动开关，可以利用具有大于数据线幅度的电压的数据线对执行初始感测操作，从而实现高速感测操作。 驱动器的分布布置使得用于过驱动的驱动器能够在感测操作中分散地提供电流，从而减小感测放大器的远和近位置的感测电压的差异。
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公开(公告)号：US07200061B2
公开(公告)日：2007-04-03
申请号：US10534049
申请日：2002-11-08
申请人： Tomonori Sekiguchi , Shinichi Miyatake , Takeshi Sakata , Riichiro Takemura , Hiromasa Noda , Kazuhiko Kajigaya
发明人： Tomonori Sekiguchi , Shinichi Miyatake , Takeshi Sakata , Riichiro Takemura , Hiromasa Noda , Kazuhiko Kajigaya
IPC分类号： G11C7/02
CPC分类号： G11C7/062 , G11C5/063 , G11C7/065 , G11C7/08 , G11C7/1078 , G11C7/1096 , G11C7/12 , G11C7/18 , G11C8/08 , G11C11/4087 , G11C11/4091 , G11C11/4094 , G11C11/4096 , G11C11/4097 , G11C29/1201 , G11C2207/002 , G11C2207/005 , H01L27/0207 , H01L27/10814 , H01L27/10882 , H01L27/10897
摘要： A direct sense amplifier of the present invention incorporates and isolates: an MOS transistor serving as a differential pair and having a gate connected to a bit line; and an MOS transistor controlled by a column select line wired between RLIO lines in a bit-line direction, and further connects a source of the MOS transistor serving as the differential pair to a common source line wired in the word-line direction. Since the direct sense amplifier only in a select map is activated by the column select line and the common source line during an read operation, power consumption is significantly reduced during the read operation. Also, since a parasitic capacitance of the MOS transistor serving as the differential pair is separated from the local IO line, a load capacity of the local IO line is reduced and the read operation is speeded up. In addition, during the read operation, a data pattern dependency of the load capacity of the local IO line is reduced and a post-manufacture test is easily made.
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93.发明申请Dynamic random access memory (DRAM) capable of canceling out complimentary noise development in plate electrodes of memory cell capacitors 有权动态随机存取存储器（DRAM）能够消除存储单元电容器的平板电极中的互补噪声发展公开(公告)号：US20050270889A1
公开(公告)日：2005-12-08
申请号：US11198357
申请日：2005-08-08
申请人： Tomonori Sekiguchi , Kazuhiko Kajigaya , Katsutaka Kimura , Riichiro Takemura , Tsugio Takahashi , Yoshitaka Nakamura
发明人： Tomonori Sekiguchi , Kazuhiko Kajigaya , Katsutaka Kimura , Riichiro Takemura , Tsugio Takahashi , Yoshitaka Nakamura
IPC分类号： G11C11/401 , G11C5/02 , G11C5/06 , G11C7/02 , G11C7/18 , G11C8/00 , G11C11/34 , G11C11/4097 , H01L21/8242 , H01L27/02 , H01L27/108
CPC分类号： G11C7/02 , G11C5/025 , G11C5/063 , G11C7/18 , G11C11/4074 , G11C11/4097 , H01L27/0207 , H01L27/0214 , H01L27/10814 , H01L27/10882 , H01L27/10885 , H01L27/10897
摘要： Disclosed herein is a dynamic RAM comprising a plurality of word lines respectively connected to address select terminals of a plurality of dynamic memory cells, a plurality of complementary bit line pairs respectively connected to input/output terminals of the plurality of dynamic memory cells and placed in directions opposite to one another, and a sense amplifier array which is supplied with an operating voltage according to an operation timing signal and comprises a plurality of latch circuits for respectively amplifying the differences in voltage between the complementary bit line pairs. In the dynamic RAM, common electrodes provided in opposing relationship to storage nodes corresponding to connecting points between address select MOSFETs and information storage capacitors of the plurality of dynamic memory cells provided on both sides with the sense amplifier array as the center are connected to one another while circuit connections in the sense amplifier array are being ensured by wiring means using the common electrodes.,
摘要翻译： 这里公开了一种动态RAM，其包括分别连接到多个动态存储单元的地址选择端的多个字线，分别连接到多个动态存储单元的输入/输出端并放置在多个动态存储单元中的多个互补位线对 方向相反，以及根据操作定时信号被提供有工作电压的读出放大器阵列，并且包括用于分别放大互补位线对之间的电压差的多个锁存电路。 在动态RAM中，以与感测放大器阵列为中心的两侧设置的多个动态存储单元的地址选择MOSFET和信息存储电容器之间的连接点对应的存储节点提供的公共电极彼此连接 而通过使用公共电极的布线装置来确保读出放大器阵列中的电路连接，
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公开(公告)号：US20050265068A1
公开(公告)日：2005-12-01
申请号：US11134476
申请日：2005-05-23
IPC分类号： H01L27/108 , G11C11/24 , G11C11/405 , G11C11/4097 , H01L21/8242 , H01L27/02
CPC分类号： G11C11/405 , G11C11/4097 , H01L27/0207 , H01L27/108 , H01L27/10814 , H01L27/10873
摘要： A semiconductor memory device that can achieve high-speed operation or that is highly integrated and simultaneously can achieve high-speed operation is provided. Transistors are disposed on both sides of diffusion layer regions to which capacitor for storing information is connected and other diffusion layer region of each transistor is connected to the same bit line. When access to a memory cell is made, two transistors are activated and the information is read. When writing operation to the memory cell is carried out, two transistors are used and electric charges are written to the capacitor.
摘要翻译： 提供了可以实现高速操作或高度集成并同时实现高速操作的半导体存储器件。 晶体管设置在扩散层区域的两侧，用于存储信息的电容器被连接到，并且每个晶体管的其它扩散层区域连接到相同的位线。 当访问存储器单元时，两个晶体管被激活并且读取该信息。 当对存储单元进行写操作时，使用两个晶体管，并将电荷写入电容器。
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公开(公告)号：US20050232044A1
公开(公告)日：2005-10-20
申请号：US11071351
申请日：2005-03-04
IPC分类号： H01L21/8242 , G11C7/02 , G11C7/06 , G11C11/401 , G11C11/409 , G11C11/4091 , H01L27/108
CPC分类号： G11C11/4091 , G11C7/065 , G11C2207/065 , H01L27/10897
摘要： Due to the further scaling down, the offset of the sense amplifier is increased and the malfunction occurs in the read operation, and thus, the yield of the chip is degraded. For its prevention, a plurality of pull-down circuits and one pull-up circuit are used to constitute the sense amplifier circuit. Also, the transistor in one of the plurality of pull-down circuits has a constant such as a channel length or a channel width larger than that of the transistor in the other pull-down circuit. Further, the pull-down circuit with a larger constant of the transistor is first activated, and then, the other pull-down circuit and the pull-up circuit are activated to perform the read operation.
摘要翻译： 由于进一步缩小，读取放大器的偏移增加，并且在读取操作中发生故障，因此芯片的产量降低。 为了防止，使用多个下拉电路和一个上拉电路来构成读出放大器电路。 此外，多个下拉电路之一中的晶体管具有诸如沟道长度或沟道宽度等于另一个下拉电路中的晶体管的沟道宽度的常数。 此外，首先激活具有较大的晶体管常数的下拉电路，然后激活另一个下拉电路和上拉电路以执行读取操作。
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公开(公告)号：US06944078B2
公开(公告)日：2005-09-13
申请号：US10892271
申请日：2004-07-16
IPC分类号： G11C7/06 , G11C11/406 , G11C11/4074 , G11C11/4091 , G11C7/00
CPC分类号： G11C7/065 , G11C5/025 , G11C5/14 , G11C7/06 , G11C7/08 , G11C11/406 , G11C11/4074 , G11C11/4091 , G11C2207/065 , H01L27/0207 , H01L27/10894
摘要： A sense amplifier capable of performing high-speed data sense operation with lower power consumption using a minuscule signal from a memory cell even in a case where a memory array voltage is reduced. A plurality of drive switches for over-driving are distributively arranged in a sense amplifier area, and a plurality of drive switches for restore operation are concentratively disposed at one end of a row of the sense amplifiers. A potential for over-driving is supplied using a meshed power line circuit. Through the use of the drive switches for over-driving, initial sense operation can be performed on data line pairs with a voltage having an amplitude larger than a data-line amplitude, allowing implementation of high-speed sense operation. The distributed arrangement of the drive switched for over-driving makes it possible to dispersively supply current in sense operation, thereby reducing a difference in sense voltage with respect to far and near positions of the sense amplifiers.
摘要翻译： 一种读出放大器即使在存储器阵列电压降低的情况下，也能够使用来自存储单元的微小信号，以较低的功耗进行高速数据检测操作。 用于过驱动的多个驱动开关被分布地布置在感测放大器区域中，并且用于恢复操作的多个驱动开关被集中地布置在一行的读出放大器的一端。 使用网状电力线电路提供过驱动的可能性。 通过使用用于过驱动的驱动开关，可以利用具有大于数据线幅度的电压的数据线对执行初始感测操作，从而实现高速感测操作。 驱动器的分布布置使得用于过驱动的驱动器能够在感测操作中分散地提供电流，从而减小感测放大器的远和近位置的感测电压的差异。
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公开(公告)号：US06943373B2
公开(公告)日：2005-09-13
申请号：US10693987
申请日：2003-10-28
申请人： Norikatsu Takaura , Hideyuki Matsuoka , Riichiro Takemura , Kousuke Okuyama , Masahiro Moniwa , Akio Nishida , Kota Funayama , Tomonori Sekiguchi
发明人： Norikatsu Takaura , Hideyuki Matsuoka , Riichiro Takemura , Kousuke Okuyama , Masahiro Moniwa , Akio Nishida , Kota Funayama , Tomonori Sekiguchi
IPC分类号： G11C11/41 , H01L21/8234 , H01L21/8244 , H01L27/00 , H01L27/06 , H01L27/088 , H01L27/10 , H01L27/11 , H01L29/10 , H01L29/72
CPC分类号： H01L27/11 , H01L27/0688 , H01L27/1104
摘要： The invention provides a semiconductor memory device comprising a plurality of word lines, a plurality of bit lines, and a plurality of static memory cells each having a first, second, third, fourth, fifth, and sixth transistors. While each of channels of the first, second, third, and fourth transistors are formed vertical against a substrate of the semiconductor memory device. Each of semiconductor regions forming a source or a drain of the fifth and sixth transistors forms a PN junction against the substrate. According to another aspect of the invention, the SRAM device of the invention has a plurality of SRAM cells, at least one of which is a vertical SRAM cell comprising at least four vertical transistors onto a substrate, and each vertical transistor includes a source, a drain, and a channel therebetween aligning in one aligning line which penetrates into the substrate surface at an angle greater than zero degree.
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公开(公告)号：US20050030783A1
公开(公告)日：2005-02-10
申请号：US10938794
申请日：2004-09-13
申请人： Tomonori Sekiguchi , Kazuhiko Kajigaya , Katsutaka Kimura , Riichiro Takemura , Tsugio Takahashi , Yoshitaka Nakamura
发明人： Tomonori Sekiguchi , Kazuhiko Kajigaya , Katsutaka Kimura , Riichiro Takemura , Tsugio Takahashi , Yoshitaka Nakamura
IPC分类号： G11C11/401 , G11C5/02 , G11C5/06 , G11C7/02 , G11C7/18 , G11C8/00 , G11C11/34 , G11C11/4097 , H01L21/8242 , H01L27/02 , H01L27/108 , G11C11/22
CPC分类号： G11C7/02 , G11C5/025 , G11C5/063 , G11C7/18 , G11C11/4074 , G11C11/4097 , H01L27/0207 , H01L27/0214 , H01L27/10814 , H01L27/10882 , H01L27/10885 , H01L27/10897
摘要： Disclosed herein is a dynamic RAM comprising a plurality of word lines respectively connected to address select terminals of a plurality of dynamic memory cells, a plurality of complementary bit line pairs respectively connected to input/output terminals of the plurality of dynamic memory cells and placed in directions opposite to one another, and a sense amplifier array which is supplied with an operating voltage according to an operation timing signal and comprises a plurality of latch circuits for respectively amplifying the differences in voltage between the complementary bit line pairs. In the dynamic RAM, common electrodes provided in opposing relationship to storage nodes corresponding to connecting points between address select MOSFETs and information storage capacitors of the plurality of dynamic memory cells provided on both sides with the sense amplifier array as the center are connected to one another while circuit connections in the sense amplifier array are being ensured by wiring means using the common electrodes.
摘要翻译： 这里公开了一种动态RAM，其包括分别连接到多个动态存储单元的地址选择端的多个字线，分别连接到多个动态存储单元的输入/输出端并放置在多个动态存储单元中的多个互补位线对 方向相反，以及根据操作定时信号被提供有工作电压的读出放大器阵列，并且包括用于分别放大互补位线对之间的电压差的多个锁存电路。 在动态RAM中，以与感测放大器阵列为中心的两侧设置的多个动态存储单元的地址选择MOSFET和信息存储电容器之间的连接点对应的存储节点提供的公共电极彼此连接 而通过使用公共电极的布线装置来确保读出放大器阵列中的电路连接。
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公开(公告)号：US20050002251A1
公开(公告)日：2005-01-06
申请号：US10892271
申请日：2004-07-16
IPC分类号： G11C7/06 , G11C11/406 , G11C11/4074 , G11C11/4091 , G11C7/02
CPC分类号： G11C7/065 , G11C5/025 , G11C5/14 , G11C7/06 , G11C7/08 , G11C11/406 , G11C11/4074 , G11C11/4091 , G11C2207/065 , H01L27/0207 , H01L27/10894
摘要： A sense amplifier capable of performing high-speed data sense operation with lower power consumption using a minuscule signal from a memory cell even in a case where a memory array voltage is reduced. A plurality of drive switches for over-driving are distributively arranged in a sense amplifier area, and a plurality of drive switches for restore operation are concentratively disposed at one end of a row of the sense amplifiers. A potential for over-driving is supplied using a meshed power line circuit. Through the use of the drive switches for over-driving, initial sense operation can be performed on data line pairs with a voltage having an amplitude larger than a data-line amplitude, allowing implementation of high-speed sense operation. The distributed arrangement of the drive switched for over-driving makes it possible to dispersively supply current in sense operation, thereby reducing a difference in sense voltage with respect to far and near positions of the sense amplifiers.
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公开(公告)号：US06671217B2
公开(公告)日：2003-12-30
申请号：US10361697
申请日：2003-02-11
IPC分类号： G11C700
CPC分类号： G11C7/065 , G11C11/4091 , G11C11/4097
摘要： A sense amplifier arrangement that achieves high-speed access and shorter cycle time when array voltage is lowered in a DRAM. In a TG clocking sense system to separate data lines between the array side and the sense amplifier side in an early stage of a sensing period, a restore amplifier RAP is added, which amplifies data lines on the array side by referring to the data in the sense amplifier, and the restore amplifier is driven by a voltage VDH higher than the array voltage VDL. As a result, high-speed sense operation of the TG clocking system is made compatible with high-speed restore operation of overdrive system, and it is possible to achieve high-speed access operation and shorter cycle time.
摘要翻译： 一种读出放大器装置，其在DRAM中降低阵列电压时实现高速存取和缩短周期时间。 在用于在感测周期的早期阶段中分离阵列侧和读出放大器侧之间的数据线的TG时钟感测系统中，添加了恢复放大器RAP，其通过参考数据线中的数据来放大阵列侧的数据线 读出放大器，并且恢复放大器由比阵列电压VDL高的电压VDH驱动。 因此，TG时钟系统的高速感测操作与过驱动系统的高速恢复操作兼容，可以实现高速存取操作和缩短周期时间。
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