公开(公告)号：US07759170B2

公开(公告)日：2010-07-20

申请号：US12710450

申请日：2010-02-23

申请人： Han-Ping Pu ,  Chien-Ping Huang ,  Cheng-Hsu Hsiao

发明人： Han-Ping Pu ,  Chien-Ping Huang ,  Cheng-Hsu Hsiao

IPC分类号： H01L21/00 ,  H01L23/34 ,  H05K7/20

CPC分类号： H01L23/473 ,  H01L21/563 ,  H01L23/3157 ,  H01L2224/16225 ,  H01L2224/48227 ,  H01L2224/73204 ,  H01L2224/73253

摘要： A semiconductor package with a heat dissipating device and a fabrication method of the semiconductor package are provided. A chip is mounted on a substrate. The heat dissipating device is mounted on the chip, and includes an accommodating room, and a first opening and a second opening that communicate with the accommodating room. An encapsulant is formed between the heat dissipating device and the substrate to encapsulate the chip. A cutting process is performed to remove a non-electrical part of structure and expose the first and second openings from the encapsulant. A cooling fluid is received in the accommodating room to absorb and dissipate heat produced by the chip. The heat dissipating device covers the encapsulant and the chip to provide a maximum heat transfer area for the semiconductor package.

摘要翻译： 提供了具有散热装置的半导体封装和半导体封装的制造方法。 芯片安装在基板上。 散热装置安装在芯片上，并且包括容纳室，以及与容纳室连通的第一开口和第二开口。 在散热装置和衬底之间形成密封剂以封装芯片。 执行切割处理以去除结构的非电气部分并且从密封剂暴露第一和第二开口。 冷却流体容纳在容纳室中以吸收和散发由芯片产生的热量。 散热装置覆盖密封剂和芯片，以为半导体封装提供最大的传热面积。

公开(公告)号：US07679178B2

公开(公告)日：2010-03-16

申请号：US11974441

申请日：2007-10-12

申请人： Han-Ping Pu ,  Chien-Ping Huang ,  Chih-Ming Huang ,  Yu-Po Wang ,  Cheng-Hsu Hsiao

发明人： Han-Ping Pu ,  Chien-Ping Huang ,  Chih-Ming Huang ,  Yu-Po Wang ,  Cheng-Hsu Hsiao

IPC分类号： H01L23/02

CPC分类号： H01L21/568 ,  H01L23/3128 ,  H01L24/16 ,  H01L24/45 ,  H01L24/48 ,  H01L24/73 ,  H01L25/105 ,  H01L2224/0554 ,  H01L2224/0557 ,  H01L2224/05571 ,  H01L2224/05573 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2224/45144 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73265 ,  H01L2225/1023 ,  H01L2225/1041 ,  H01L2225/1058 ,  H01L2924/00014 ,  H01L2924/01079 ,  H01L2924/15192 ,  H01L2924/15311 ,  H01L2924/16151 ,  H01L2924/16195 ,  H01L2924/18161 ,  H01L2924/19107 ,  H01L2924/00012 ,  H01L2924/00 ,  H01L2224/05599 ,  H01L2224/0555 ,  H01L2224/0556

摘要： A semiconductor package on which a semiconductor device can be stacked and fabrication method thereof are provided. The fabrication method includes the steps of mounting and electrically connecting at least one semiconductor chip on the substrate, mounting an electrical connecting structure consisting of an upper layer circuit board and a lower layer circuit board on the substrate and electrically connecting the electrical connecting structure to the substrate, where the semiconductor chip is received in a receiving space formed in the electrical connecting structure; forming an encapsulant on the substrate encapsulating the semiconductor chip and the electrical connecting structure, and after the encapsulant is formed, exposing top surface of the upper layer circuit board with a plurality of solder pads from the encapsulant to allow at least one semiconductor device to electrically connect the upper layer circuit board so as to form a stack structure.

摘要翻译： 提供半导体器件可堆叠的半导体封装件及其制造方法。 该制造方法包括以下步骤：在基板上安装和电连接至少一个半导体芯片，将由上层电路板和下层电路板组成的电连接结构安装在基板上，并将电连接结构电连接到 衬底，其中所述半导体芯片被容纳在形成在所述电连接结构中的接收空间中; 在封装半导体芯片和电连接结构的基板上形成密封剂，并且在形成密封剂之后，用来自密封剂的多个焊盘将上层电路板的顶表面曝光，以允许至少一个半导体器件电 连接上层电路板，形成堆叠结构。

公开(公告)号：US20090020864A1

公开(公告)日：2009-01-22

申请号：US11779192

申请日：2007-07-17

申请人： Han-Ping Pu ,  Mirng-Ji Lii

发明人： Han-Ping Pu ,  Mirng-Ji Lii

IPC分类号： H01L23/22 ,  H01L21/00

CPC分类号： H01L21/568 ,  H01L21/561 ,  H01L21/6835 ,  H01L23/3107 ,  H01L24/13 ,  H01L24/19 ,  H01L24/96 ,  H01L24/97 ,  H01L2224/0401 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/13 ,  H01L2224/13099 ,  H01L2224/16 ,  H01L2224/20 ,  H01L2224/97 ,  H01L2924/00013 ,  H01L2924/01013 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01078 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2224/82 ,  H01L2224/29099 ,  H01L2924/00

摘要： A method of forming a package structure with reduced damage to semiconductor dies is provided. The method includes providing a die comprising bond pads on a top surface of the die; forming bumps on the bond pads of the die, wherein the bumps have top surfaces higher than the top surface of the die; mounting the die on a chip carrier, wherein the bumps are attached to the chip carrier; molding the die onto the chip carrier with a molding compound; de-mounting the chip carrier from the die; and forming redistribution traces over, and electrically connected to, the bumps of the die.

摘要翻译： 提供一种形成具有对半导体管芯的损伤减小的封装结构的方法。 所述方法包括提供在所述管芯的顶表面上包括接合焊盘的管芯; 在所述模具的接合焊盘上形成凸起，其中所述凸起具有高于所述模具的顶表面的顶表面; 将所述管芯安装在芯片载体上，其中所述凸块附接到所述芯片载体上; 用模塑料将模具成型到芯片载体上; 将芯片载体从芯片上拆下; 以及在模具的凸起上形成并电连接到模具的凸块上的再分布迹线。

公开(公告)号：US20080296764A1

公开(公告)日：2008-12-04

申请号：US11807522

申请日：2007-05-29

申请人： Kuo-Chin Chang ,  Han-Ping Pu ,  Pei-Haw Tsao

发明人： Kuo-Chin Chang ,  Han-Ping Pu ,  Pei-Haw Tsao

IPC分类号： H01L23/488 ,  H01L21/44

CPC分类号： H01L24/11 ,  H01L24/81 ,  H01L2224/0231 ,  H01L2224/0401 ,  H01L2224/114 ,  H01L2224/1147 ,  H01L2224/1148 ,  H01L2224/116 ,  H01L2224/11902 ,  H01L2224/13019 ,  H01L2224/13076 ,  H01L2224/13078 ,  H01L2224/13099 ,  H01L2224/131 ,  H01L2224/81801 ,  H01L2924/01004 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01015 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01075 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01327 ,  H01L2924/014 ,  H01L2924/14 ,  H01L2924/181 ,  H01L2924/00

摘要： An enhanced wafer level chip scale packaging (WLCSP) copper electrode post is described having one or more pins that protrude from the top of the electrode post. When the solder ball is soldered onto the post, the pins are encapsulated within the solder material. The pins not only add shear strength to the soldered joint between the solder ball and the electrode post but also create a more reliable electrical connection due to the increased surface area between the electrode post/pin combination and the solder ball. Moreover, creating an irregularly shaped solder joint retards the propagation of cracks that may form in the intermetal compounds (IMC) layer formed at the solder joint.

摘要翻译： 描述了增强的晶片级芯片级封装（WLCSP）铜电极柱，其具有从电极柱的顶部突出的一个或多个引脚。 当焊球焊接到柱上时，引脚被封装在焊料材料内。 引脚不仅在焊球和电极柱之间的焊接接头上增加剪切强度，而且由于电极柱/销组合和焊球之间的表面积增加，也产生更可靠的电连接。 此外，产生不规则形状的焊点阻碍了可能在焊接接头形成的金属间化合物（IMC）层中形成的裂纹的传播。

公开(公告)号：US20080286938A1

公开(公告)日：2008-11-20

申请号：US11798432

申请日：2007-05-14

申请人： Han-Ping Pu ,  Bai-Yao Lou ,  Dean Wang ,  Ching-Wen Hsiao ,  Kai-Ming Ching ,  Chen-Cheng Kuo ,  Wen-Chih Chiou ,  Ding-Chung Lu ,  Shang-Yun Hou

发明人： Han-Ping Pu ,  Bai-Yao Lou ,  Dean Wang ,  Ching-Wen Hsiao ,  Kai-Ming Ching ,  Chen-Cheng Kuo ,  Wen-Chih Chiou ,  Ding-Chung Lu ,  Shang-Yun Hou

IPC分类号： H01L21/30

CPC分类号： H01L21/78 ,  H01L2224/05001 ,  H01L2224/05022 ,  H01L2224/05023 ,  H01L2224/051 ,  H01L2224/05572 ,  H01L2224/056 ,  H01L2224/11 ,  H01L2924/00014

摘要： A method for packaging a semiconductor device disclosed. A substrate comprising a plurality of dies, separated by scribe line areas respectively is provided, wherein at least one layer is overlying the substrate. A portion of the layer within the scribe lines area is removed by photolithography and etching to form openings. The substrate is sawed along the scribe line areas, passing the openings. In alternative embodiment, a first substrate comprising a plurality of first dies separated by first scribe line areas respectively is provided, wherein at least one first structural layer is overlying the first substrate. The first structural layer is patterned to form first openings within the first scribe line areas. A second substrate comprising a plurality of second dies separated by second scribe line areas respectively is provided, wherein at least one second structural layer is overlying the substrate. The second structural layer is patterned to form second openings within the second scribe line areas. The first substrate and the second substrate are bonded to form a stack structure. The stack structure is cut along the first and second scribe line areas, passing the first and second openings.

摘要翻译： 一种封装半导体器件的方法。 提供了包括分别由划线区域分隔的多个管芯的衬底，其中至少一层覆盖衬底。 通过光刻和蚀刻去除划线部分内的层的一部分以形成开口。 沿着划线区域锯切基板，通过开口。 在替代实施例中，提供了包括分别由第一划线区域分开的多个第一裸片的第一衬底，其中至少一个第一结构层覆盖在第一衬底上。 图案化第一结构层以在第一划线区域内形成第一开口。 提供了包括分别由第二划线区域分隔的多个第二模具的第二衬底，其中至少一个第二结构层覆盖在衬底上。 图案化第二结构层以在第二划线区域内形成第二开口。 第一基板和第二基板被接合以形成堆叠结构。 沿着第一和第二划线区域切割堆叠结构，使第一和第二开口通过。

公开(公告)号：US20080138935A1

公开(公告)日：2008-06-12

申请号：US11891134

申请日：2007-08-08

申请人： Han-Ping Pu ,  Chien-Ping Huang ,  Cheng-Hsu Hsiao

发明人： Han-Ping Pu ,  Chien-Ping Huang ,  Cheng-Hsu Hsiao

IPC分类号： H01L21/00

CPC分类号： H01L21/561 ,  H01L21/568 ,  H01L23/3114 ,  H01L24/19 ,  H01L24/96 ,  H01L24/97 ,  H01L2224/0401 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/16225 ,  H01L2224/20 ,  H01L2224/97 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01046 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/15311 ,  H01L2924/18161 ,  H01L2924/18162 ,  H01L2924/351 ,  H01L2224/82 ,  H01L2924/00

摘要： A chip scale package structure and a method for fabricating the same are disclosed. The method includes forming metal pads on a predetermined part of a carrier; mounting chips on the carrier, each of the chips having a plurality of conductive bumps soldered to the metal pads; forming an encapsulant on the carrier to encapsulate the chips and the conductive bumps; removing the carrier to expose the metal pads and even the metal pads with a surface of the encapsulant; forming on the encapsulant a plurality of first conductive traces electrically connected to the metal pads; applying a solder mask on the first conductive traces, and forming a plurality of openings on the solder mask to expose a predetermined part of the first conductive traces; forming a plurality of conductive elements on the predetermined part; and cutting the encapsulant to form a plurality of chip scale package structures.

摘要翻译： 公开了一种芯片级封装结构及其制造方法。 该方法包括在载体的预定部分上形成金属垫; 在载体上安装芯片，每个芯片具有焊接到金属焊盘的多个导电凸块; 在载体上形成密封剂以封装芯片和导电凸块; 移除载体以暴露金属垫和甚至具有密封剂表面的金属垫; 在所述密封剂上形成电连接到所述金属焊盘的多个第一导电迹线; 在所述第一导电迹线上施加焊接掩模，以及在所述焊接掩模上形成多个开口以暴露所述第一导电迹线的预定部分; 在所述预定部分上形成多个导电元件; 以及切割所述密封剂以形成多个芯片级封装结构。

公开(公告)号：US20080012111A1

公开(公告)日：2008-01-17

申请号：US11592046

申请日：2006-11-01

申请人： Han-Ping Pu ,  Cheng-Hsu Hsiao

发明人： Han-Ping Pu ,  Cheng-Hsu Hsiao

IPC分类号： H01L23/28 ,  H01L21/44 ,  H01L23/02

CPC分类号： H01L23/3128 ,  H01L24/48 ,  H01L24/73 ,  H01L24/97 ,  H01L25/105 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2224/32245 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/48247 ,  H01L2224/73265 ,  H01L2224/97 ,  H01L2225/1005 ,  H01L2225/1023 ,  H01L2225/1029 ,  H01L2225/1058 ,  H01L2225/1064 ,  H01L2924/00014 ,  H01L2924/01033 ,  H01L2924/01082 ,  H01L2924/15174 ,  H01L2924/15311 ,  H01L2924/15331 ,  H01L2924/181 ,  H01L2924/1815 ,  H01L2224/81 ,  H01L2224/85 ,  H01L2924/00012 ,  H01L2924/00 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

摘要： The present invention provides a semiconductor package and a fabrication method thereof. The method includes the steps of: providing a chip carrier module having a plurality of chip carriers, disposing a plurality of electrical connecting points on the chip carriers, performing chip mounting and molding on the chip carrier module to form an encapsulant encapsulating the semiconductor chip, exposing the electrical connecting points from the encapsulant; forming a patterned circuit layer on the encapsulant, electrically connecting the patterned circuit layer to the electrical connecting points, cutting and separating the chip carriers to form a plurality of semiconductor packages each having a circuit layer formed on the encapsulant such that the circuit layer provides extra electrical connecting points and thereby enhances electrical performance of electrical products. During a package stacking process, no package is limited by the design of another package below.

摘要翻译： 本发明提供半导体封装及其制造方法。 该方法包括以下步骤：提供具有多个芯片载体的芯片载体模块，在芯片载体上布置多个电连接点，在芯片载体模块上执行芯片安装和模制以形成封装半导体芯片的密封剂， 将电连接点暴露于密封剂; 在所述密封剂上形成图案化电路层，将所述图案化电路层电连接到所述电连接点，切割和分离所述芯片载体以形成多个半导体封装，每个半导体封装具有形成在所述密封剂上的电路层，使得所述电路层提供额外的 电连接点，从而提高电气产品的电气性能。 在包装堆垛过程中，没有包装受下面另一包装的设计限制。

公开(公告)号：US20070249094A1

公开(公告)日：2007-10-25

申请号：US11820366

申请日：2007-06-19

申请人： Han-Ping Pu

发明人： Han-Ping Pu

IPC分类号： H01L21/50

CPC分类号： H05K1/141 ,  H01L24/97 ,  H01L25/03 ,  H01L25/0657 ,  H01L2224/0554 ,  H01L2224/0557 ,  H01L2224/05571 ,  H01L2224/05573 ,  H01L2224/16225 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/73253 ,  H01L2224/97 ,  H01L2225/06517 ,  H01L2225/06582 ,  H01L2225/06589 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01033 ,  H01L2924/01082 ,  H01L2924/15311 ,  H05K3/284 ,  H05K3/3436 ,  H05K2201/10515 ,  H05K2201/10674 ,  H05K2201/10689 ,  H01L2224/81 ,  H01L2224/05599 ,  H01L2224/0555 ,  H01L2224/0556

摘要： A multi-chip semiconductor package and a fabrication method thereof are provided. At least one first chip is mounted on and electrically connected to an upper surface of a substrate via solder bumps. A preformed package structure having a second chip and a first encapsulation body is mounted on the upper surface of the substrate, wherein outer leads of the preformed package structure are exposed from the first encapsulation body and electrically connected to the upper surface of the substrate. The first encapsulation body, outer leads and substrate form a space where the first chip is received, and a gap is present between the first chip and the first encapsulation body. A second encapsulation body is formed on the upper surface of the substrate to encapsulate the first chip, solder bumps and preformed package structure. A plurality of solder balls are implanted on the lower surface of the substrate.

摘要翻译： 提供一种多芯片半导体封装及其制造方法。 至少一个第一芯片通过焊料凸块安装在基板的上表面上并电连接到基板的上表面。 具有第二芯片和第一封装体的预制封装结构安装在基板的上表面上，其中预成型封装结构的外引线从第一封装体露出并电连接到基板的上表面。 第一封装体，外引线和衬底形成接收第一芯片的空间，并且在第一芯片和第一封装体之间存在间隙。 第二封装体形成在衬底的上表面上，以封装第一芯片，焊料凸块和预成型封装结构。 在基板的下表面上注入多个焊球。

公开(公告)号：US20070246811A1

公开(公告)日：2007-10-25

申请号：US11732853

申请日：2007-04-04

申请人： Fang-Lin Tsai ,  Ho-Yi Tsai ,  Han-Ping Pu ,  Cheng-Hsu Hsiao

发明人： Fang-Lin Tsai ,  Ho-Yi Tsai ,  Han-Ping Pu ,  Cheng-Hsu Hsiao

IPC分类号： H01L23/02 ,  H01L21/00

CPC分类号： H01L25/105 ,  H01L23/49811 ,  H01L23/49838 ,  H01L24/73 ,  H01L25/50 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73265 ,  H01L2225/1023 ,  H01L2225/1058 ,  H01L2924/01077 ,  H01L2924/15311 ,  H01L2924/15331 ,  H01L2924/00014 ,  H01L2924/00012 ,  H01L2924/00

摘要： A stack structure of semiconductor packages and a method for fabricating the stack structure are provided. A plurality of electrical connection pads and dummy pads are formed on a surface of a substrate of an upper semiconductor package and at positions corresponding to those around an encapsulant of a lower semiconductor package. Solder balls are implanted to the electrical connection pads and the dummy pads. The upper semiconductor package is mounted on the lower semiconductor package. The upper semiconductor package is electrically connected to the lower semiconductor package by the solder balls implanted to the electrical connection pads, and the encapsulant of the lower semiconductor package is surrounded and confined by the solder balls implanted to the dummy pads. Thereby, the upper semiconductor package is properly and securely positioned on the lower semiconductor package, without the occurrence of misalignment between the upper and lower semiconductor packages.

摘要翻译： 提供半导体封装的堆叠结构以及制造叠层结构的方法。 在上半导体封装的衬底的表面上和与下半导体封装的密封剂周围的位置对应的位置处形成多个电连接焊盘和虚拟焊盘。 将焊球植入电连接焊盘和虚拟焊盘。 上半导体封装安装在下半导体封装上。 上半导体封装通过注入电连接焊盘的焊球电连接到下半导体封装，并且下半导体封装的密封剂被植入到虚拟焊盘中的焊球围绕并限制。 因此，上半导体封装被适当且牢固地定位在下半导体封装上，而不会发生上下半导体封装之间的未对准。

公开(公告)号：US20070200228A1

公开(公告)日：2007-08-30

申请号：US11647832

申请日：2006-12-29

申请人： Han-Ping Pu ,  Chien-Ping Huang ,  Cheng-Hsu Hsiao

发明人： Han-Ping Pu ,  Chien-Ping Huang ,  Cheng-Hsu Hsiao

IPC分类号： H01L23/34

CPC分类号： H01L23/473 ,  H01L21/563 ,  H01L23/3157 ,  H01L2224/16225 ,  H01L2224/48227 ,  H01L2224/73204 ,  H01L2224/73253

摘要： A semiconductor package with a heat dissipating device and a fabrication method of the semiconductor package are provided. A chip is mounted on a substrate. The heat dissipating device is mounted on the chip, and includes an accommodating room, and a first opening and a second opening that communicate with the accommodating room. An encapsulant is formed between the heat dissipating device and the substrate to encapsulate the chip. A cutting process is performed to remove a non-electrical part of structure and expose the first and second openings from the encapsulant. A cooling fluid is received in the accommodating room to absorb and dissipate heat produced by the chip. The heat dissipating device covers the encapsulant and the chip to provide a maximum heat transfer area for the semiconductor package.

摘要翻译： 提供了具有散热装置的半导体封装和半导体封装的制造方法。 芯片安装在基板上。 散热装置安装在芯片上，并且包括容纳室，以及与容纳室连通的第一开口和第二开口。 在散热装置和衬底之间形成密封剂以封装芯片。 执行切割处理以去除结构的非电气部分，并使第一和第二开口与密封剂暴露。 冷却流体容纳在容纳室中以吸收和散发由芯片产生的热量。 散热装置覆盖密封剂和芯片，以为半导体封装提供最大的传热面积。