公开(公告)号：US09601600B2

公开(公告)日：2017-03-21

申请号：US14855793

申请日：2015-09-16

Applicant: United Microelectronics Corp.

Inventor： Yu-Hsiang Hung ,  Ssu-I Fu ,  Chung-Fu Chang ,  Yen-Liang Wu ,  Cho-Han Fan ,  Chien-Ting Lin

IPC: H01L21/8238 ,  H01L29/66 ,  H01L29/78 ,  H01L29/165

CPC classification number: H01L29/66795 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/823821 ,  H01L29/165 ,  H01L29/66636 ,  H01L29/7834 ,  H01L29/7848 ,  H01L29/785

Abstract: A process for fabricating a fin-type field effect transistor (FinFET) structure is described. A semiconductor substrate is patterned to form a fin. A spacer is formed on the sidewall of the fin. A portion of the fin is removed, such that the spacer and the surface of the remaining fin together define a cavity. A piece of a semiconductor compound is formed from the cavity, wherein the upper portion of the piece of the semiconductor compound laterally extends over the spacer.

公开(公告)号：US20160380081A1

公开(公告)日：2016-12-29

申请号：US14818322

申请日：2015-08-05

Applicant: United Microelectronics Corp.

Inventor： Chih-Kai Hsu ,  Yu-Hsiang Hung ,  Ssu-I Fu ,  Jyh-Shyang Jenq

IPC: H01L29/66 ,  H01L29/78 ,  H01L21/762

CPC classification number: H01L29/66795 ,  H01L21/76224 ,  H01L29/7851

Abstract: A FinFET includes a substrate. Numerous fin structures are defined on the substrate. A gate structure crosses each fin structure. Two epitaxial layers are disposed at two side of the gate structure, respectively. Each epitaxial layer has a top surface including a second recessed and protruding profile. A contact plug contacts the second recessed and protruding profile. The second recessed and protruding profile increases the contact area between the contact plug and the epitaxial layer.

Abstract translation: FinFET包括衬底。 在衬底上限定了许多翅片结构。 栅极结构跨越每个鳍结构。 两个外延层分别设置在栅极结构的两侧。 每个外延层具有包括第二凹入和突出轮廓的顶表面。 接触插头接触第二凹入和突出的轮廓。 第二凹入和突出的轮廓增加了接触插塞和外延层之间的接触面积。

公开(公告)号：US20160358827A1

公开(公告)日：2016-12-08

申请号：US15241077

申请日：2016-08-19

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chih-Kai Hsu ,  Ssu-I Fu ,  Yu-Hsiang Hung ,  Wei-Chi Cheng ,  Jyh-Shyang Jenq

IPC: H01L21/84 ,  H01L21/306 ,  H01L21/02 ,  H01L21/311 ,  H01L29/66 ,  H01L21/762 ,  H01L21/308

CPC classification number: H01L21/845 ,  H01L21/02238 ,  H01L21/02365 ,  H01L21/02367 ,  H01L21/762 ,  H01L21/76202 ,  H01L21/7624 ,  H01L27/1211 ,  H01L29/0649 ,  H01L29/0653 ,  H01L29/1054 ,  H01L29/66795 ,  H01L29/785

Abstract: A method of forming a fin-shaped structure includes the following step. A substrate having a first area and a second area is provided. An epitaxial structure is formed in the first area. An epitaxial structure is formed in the second area after the epitaxial structure in the first area is formed, wherein the surface area of the epitaxial structure in the first area is different from the surface area of the epitaxial structure in the second area.

Abstract translation: 形成翅片状结构的方法包括以下步骤。 提供具有第一区域和第二区域的衬底。 在第一区域中形成外延结构。 在形成第一区域中的外延结构之后，在第二区域中形成外延结构，其中第一区域中的外延结构的表面积与第二区域中的外延结构的表面积不同。

公开(公告)号：US09443954B2

公开(公告)日：2016-09-13

申请号：US15009808

申请日：2016-01-28

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chih-Kai Hsu ,  Yu-Hsiang Hung ,  Ssu-I Fu ,  Jyh-Shyang Jenq

IPC: H01L27/02 ,  H01L29/66 ,  H01L21/8238 ,  H01L21/28

CPC classification number: H01L29/66545 ,  H01L21/28088 ,  H01L21/823842 ,  H01L27/092 ,  H01L27/0922 ,  H01L29/4966

Abstract: The present invention provides a method for forming a semiconductor device having a metal gate. The method includes firstly, a substrate is provided, and a first semiconductor device and a second semiconductor device are formed on the substrate, having a first gate trench and a second trench respectively. Next, a bottom barrier layer is formed in the first gate trench and a second trench. Afterwards, a first pull back step is performed, to remove parts of the bottom barrier layer, and a first work function metal layer is then formed in the first gate trench. Next, a second pull back step is performed, to remove parts of the first work function metal layer, wherein the topmost portion of the first work function metal layer is lower than the openings of the first gate trench and the second gate trench.

Abstract translation: 本发明提供一种形成具有金属栅极的半导体器件的方法。 该方法首先包括衬底，并且在衬底上形成第一半导体器件和第二半导体器件，分别具有第一栅极沟槽和第二沟槽。 接下来，在第一栅极沟槽和第二沟槽中形成底部阻挡层。 之后，执行第一回拉步骤以去除底部阻挡层的部分，然后在第一栅极沟槽中形成第一功函数金属层。 接下来，执行第二拉回步骤以去除第一功函数金属层的部分，其中第一功函数金属层的最顶部比第一栅沟槽和第二栅沟的开口低。

公开(公告)号：US20160204197A1

公开(公告)日：2016-07-14

申请号：US14612300

申请日：2015-02-03

Applicant: United Microelectronics Corp.

Inventor： En-Chiuan Liou ,  Ssu-I Fu ,  Chia-Lin Lu ,  Shih-Hung Tsai ,  Chih-Wei Yang ,  Chia-Ching Lin ,  Chia-Hsun Tseng ,  Rai-Min Huang

IPC: H01L29/06 ,  H01L21/762

CPC classification number: H01L29/0684 ,  H01L21/76 ,  H01L21/762 ,  H01L21/76232 ,  H01L27/1211 ,  H01L29/0649 ,  H01L29/6681 ,  H01L29/7846 ,  H01L29/7851

Abstract: The present invention provides a semiconductor structure, including a substrate, a shallow trench isolation (STI) disposed in the substrate, a plurality of first fin structures disposed in the substrate, where each first fin structure and the substrate have same material, and a plurality of second fin structures disposed in the STI, where each second fin structure and the STI have same material.

Abstract translation: 本发明提供一种半导体结构，包括基板，设置在基板中的浅沟槽隔离（STI），设置在基板中的多个第一翅片结构，其中每个第一翅片结构和基板具有相同的材料，以及多个 设置在STI中的第二鳍结构，其中每个第二鳍结构和STI具有相同的材料。

公开(公告)号：US09349833B1

公开(公告)日：2016-05-24

申请号：US14614416

申请日：2015-02-05

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Yu-Hsiang Hung ,  Chao-Hung Lin ,  Ying-Tsung Chen ,  Chih-Kai Hsu ,  Ssu-I Fu ,  Jyh-Shyang Jenq ,  Shih-Hung Tsai

IPC: H01L21/8234 ,  H01L29/66 ,  H01L21/311 ,  H01L21/28 ,  H01L27/088 ,  H01L23/535

CPC classification number: H01L29/6656 ,  H01L21/823468 ,  H01L21/823475 ,  H01L23/485 ,  H01L27/088 ,  H01L29/4983 ,  H01L29/6653 ,  H01L29/66545 ,  H01L29/78 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A semiconductor device includes a plurality of gate structures, a source/drain region, a first dielectric layer, and a floating spacer. The gate structures are disposed on a substrate, and each gate structure includes a gate electrode, a capping layer and a spacer surrounding the gate electrode and the capping layer. The source/drain region is disposed at two sides of the gate electrode. The first dielectric layer is disposed on the substrate and has a height being less than a height of the gate electrode. The floating spacer is disposed on a side wall of the spacer, and also on the first dielectric layer.

Abstract translation: 半导体器件包括多个栅极结构，源极/漏极区，第一电介质层和浮置间隔物。 栅极结构设置在衬底上，并且每个栅极结构包括栅电极，覆盖层和围绕栅电极和覆盖层的间隔物。 源极/漏极区域设置在栅电极的两侧。 第一介电层设置在基板上，其高度小于栅电极的高度。 浮动间隔件设置在间隔件的侧壁上，也位于第一介电层上。

公开(公告)号：US09349822B2

公开(公告)日：2016-05-24

申请号：US14543914

申请日：2014-11-18

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chih-Wei Yang ,  Yu-Feng Liu ,  Jian-Cun Ke ,  Chia-Fu Hsu ,  En-Chiuan Liou ,  Ssu-I Fu ,  Chi-Mao Hsu ,  Nien-Ting Ho ,  Yu-Ru Yang ,  Yu-Ping Wang ,  Chien-Ming Lai ,  Yi-Wen Chen ,  Yu-Ting Tseng ,  Ya-Huei Tsai ,  Chien-Chung Huang ,  Tsung-Yin Hsieh ,  Hung-Yi Wu

IPC: H01L29/49 ,  H01L27/088 ,  H01L21/8234 ,  H01L21/28 ,  H01L21/321 ,  H01L27/092

CPC classification number: H01L29/4966 ,  H01L21/28088 ,  H01L21/321 ,  H01L21/823431 ,  H01L21/82345 ,  H01L27/088 ,  H01L29/517 ,  H01L29/66545

Abstract: A method for fabricating semiconductor device is disclosed. The method includes the steps of: providing a substrate having an interlayer dielectric (ILD) layer thereon; forming a first recess, a second recess, and a third recess in the ILD layer; forming a material layer on the ILD layer and in the first recess, the second recess, and the third recess; performing a first treatment on the material layer in the first recess; and performing a second treatment on the material layer in the first recess and second recess.

Abstract translation: 公开了半导体器件的制造方法。 该方法包括以下步骤：提供其上具有层间电介质（ILD）层的衬底; 在ILD层中形成第一凹槽，第二凹槽和第三凹槽; 在所述ILD层和所述第一凹部，所述第二凹部和所述第三凹部中形成材料层; 对所述第一凹部中的所述材料层进行第一处理; 以及对所述第一凹部和所述第二凹部中的所述材料层进行第二处理。

公开(公告)号：US09318609B2

公开(公告)日：2016-04-19

申请号：US14620209

申请日：2015-02-12

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Yu-Hsiang Hung ,  Ssu-I Fu ,  Chung-Fu Chang ,  Cheng-Guo Chen ,  Chien-Ting Lin

IPC: H01L27/01 ,  H01L29/78 ,  H01L29/66 ,  H01L21/8234 ,  H01L21/84 ,  H01L27/12 ,  H01L29/06 ,  H01L29/161

CPC classification number: H01L29/7851 ,  H01L21/8234 ,  H01L21/845 ,  H01L27/1211 ,  H01L29/0653 ,  H01L29/161 ,  H01L29/66795 ,  H01L29/6681 ,  H01L29/7848 ,  H01L29/7855

Abstract: A semiconductor device includes a fin structure, an isolation structure, a gate structure and an epitaxial structure. The fin structure protrudes from the surface of the substrate and includes a top surface and two sidewalls. The isolation structure surrounds the fin structure. The gate structure overlays the top surface and the two sidewalls of a portion of the fin structure, and covers a portion of the isolation structure. The isolation structure under the gate structure has a first top surface, and the isolation structure at two sides of the gate structure has a second top surface. The first top surface is higher than the second top surface. The epitaxial layer is disposed at one side of the gate structure and is in direct contact with the fin structure.

Abstract translation: 半导体器件包括鳍结构，隔离结构，栅极结构和外延结构。 翅片结构从衬底的表面突出并且包括顶表面和两个侧壁。 隔离结构围绕翅片结构。 栅极结构覆盖鳍结构的一部分的顶表面和两个侧壁，并且覆盖隔离结构的一部分。 栅极结构下的隔离结构具有第一顶表面，并且栅极结构两侧的隔离结构具有第二顶表面。 第一顶面高于第二顶面。 外延层设置在栅极结构的一侧并与鳍结构直接接触。

公开(公告)号：US09224864B1

公开(公告)日：2015-12-29

申请号：US14463676

申请日：2014-08-20

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Yen-Liang Wu ,  Chung-Fu Chang ,  Yu-Hsiang Hung ,  Wen-Jiun Shen ,  Ssu-I Fu ,  Man-Ling Lu ,  Chia-Jong Liu ,  Yi-Wei Chen

IPC: H01L21/00 ,  H01L21/84 ,  H01L29/78 ,  H01L29/66

CPC classification number: H01L29/7848 ,  H01L29/0673 ,  H01L29/1054 ,  H01L29/161 ,  H01L29/66545 ,  H01L29/66795 ,  H01L29/775 ,  H01L29/785 ,  H01L29/7854

Abstract: A semiconductor device includes a fin structure, an insulating structure, a protruding structure, an epitaxial structure, and a gate structure. The fin structure and the insulating structure are disposed on the substrate. The protruding structure is in direct contact with the substrate and partially protrudes from the insulating structure, and the protruding structure is the fin structure. The epitaxial structure is disposed on a top surface of the fin structure and completely covers the top surface of the fin structure. In addition, the epitaxial structure has a curved top surface. The gate structure covers the fin structure and the epitaxial structure.

Abstract translation: 半导体器件包括鳍结构，绝缘结构，突出结构，外延结构和栅极结构。 翅片结构和绝缘结构设置在基板上。 突出结构与基板直接接触，并从绝缘结构部分突出，突出结构为翅片结构。 外延结构设置在翅片结构的顶表面上并完全覆盖翅片结构的顶表面。 此外，外延结构具有弯曲的顶表面。 栅极结构覆盖鳍结构和外延结构。

公开(公告)号：US20150364568A1

公开(公告)日：2015-12-17

申请号：US14341838

申请日：2014-07-27

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Yen-Liang Wu ,  Chung-Fu Chang ,  Yu-Hsiang Hung ,  Ssu-I Fu ,  Man-Ling Lu ,  Chia-Jong Liu ,  Wen-Jiun Shen ,  Yi-Wei Chen

IPC: H01L29/66

CPC classification number: H01L29/6656 ,  H01L21/26586 ,  H01L29/6659 ,  H01L29/66636 ,  H01L29/7834

Abstract: A fabrication method of a semiconductor structure includes the following steps. First of all, a gate structure is provided on a substrate, and a first material layer is formed on the substrate and the gate structure. Next, boron dopant is implanted to the substrate, at two sides of the gate structure, to form a first doped region, and P type conductive dopant is implanted to the substrate, at the two sides of the gate structure, to form a second doped region. As following, a second material layer is formed on the first material layer. Finally, the second material layer, the first material layer and the substrate at the two sides of the gate structure are etched sequentially, and a recess is formed in the substrate, at the two sides of the gate structure, wherein the recess is positioned within the first doped region.

Abstract translation: 半导体结构的制造方法包括以下步骤。 首先，在基板上设置栅极结构，在基板和栅极结构上形成第一材料层。 接下来，在栅极结构的两侧将硼掺杂剂注入到衬底中以形成第一掺杂区，并且在栅极结构的两侧将P型导电掺杂剂注入到衬底中，以形成第二掺杂区 地区。 如下，在第一材料层上形成第二材料层。 最后，栅极结构的两侧的第二材料层，第一材料层和衬底被顺序地蚀刻，并且在栅极结构的两侧在衬底中形成凹部，其中凹部位于 第一掺杂区域。