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128 条记录 (耗时 0.044 秒)

    Two-wire AC switch
    91.
    发明授权
    Two-wire AC switch 有权
    双线交流开关

    公开(公告)号：US08593068B2

    公开(公告)日：2013-11-26

    申请号：US13032297

    申请日：2011-02-22

    申请人： Shingo Hashizume ,  Ayanori Ikoshi ,  Hiroto Yamagiwa ,  Yasuhiro Uemoto ,  Manabu Yanagihara

    发明人： Shingo Hashizume ,  Ayanori Ikoshi ,  Hiroto Yamagiwa ,  Yasuhiro Uemoto ,  Manabu Yanagihara

    IPC分类号： H05B39/02

    CPC分类号： H01L29/808 ,  H01L29/2003 ,  H01L29/42316 ,  H03K17/12 ,  H03K2217/0009

    摘要： A two-wire AC switch suppressing heat from a bidirectional switch element inside the switch is provided. The two-wire AC switch 100a connected between an AC power supply 101 and a load 102 includes: a bidirectional switch element 103 which flows passing current bi-directionally, selects whether to flow or block the current, is connected in series with the AC power supply 101 and the load 102 to form a closed-loop circuit, and is made of a group-III nitride semiconductor; a full-wave rectifier 104 performing full-wave rectification on power supplied from the AC power supply 101; a power supply circuit 105 smoothing a voltage after the full-wave rectification to generate DC power; a first gate drive circuit 107 and a second gate drive circuit 108 each outputting a control signal to the bidirectional switch element 103; and a control circuit 106 controlling the first and second gate drive circuits 107 and 108.

    摘要翻译： 提供一种抑制来自开关内的双向开关元件的热量的二线交流开关。 连接在交流电源101和负载102之间的二线交流开关100a包括：双向开关元件103，其双向开关元件103，其双向开关元件103，其双向开关元件103，其双向开关元件103，其双向开关元件103，其双向开关元件103， 电源101和负载102以形成闭环电路，并且由III族氮化物半导体制成; 全波整流器104对从AC电源101提供的电力进行全波整流; 电源电路105，对全波整流后的电压进行平滑化，生成直流电力; 每个向双向开关元件103输出控制信号的第一栅极驱动电路107和第二栅极驱动电路108; 以及控制电路106，其控制第一和第二栅极驱动电路107和108。

    Nitride semiconductor device and method for fabricating the same
    93.
    发明授权
    Nitride semiconductor device and method for fabricating the same 有权
    氮化物半导体器件及其制造方法

    公开(公告)号：US08129748B2

    公开(公告)日：2012-03-06

    申请号：US11878352

    申请日：2007-07-24

    申请人： Yasuhiro Uemoto ,  Masahiro Hikita ,  Tetsuzo Ueda ,  Tsuyoshi Tanaka ,  Daisuke Ueda

    发明人： Yasuhiro Uemoto ,  Masahiro Hikita ,  Tetsuzo Ueda ,  Tsuyoshi Tanaka ,  Daisuke Ueda

    IPC分类号： H01L29/66

    CPC分类号： H01L29/7786 ,  H01L29/1066 ,  H01L29/2003 ,  H01L29/4175 ,  H01L29/7783

    摘要： A nitride semiconductor device includes: a first nitride semiconductor layer; a second nitride semiconductor layer formed on the first nitride semiconductor layer and having a wider band gap than the first nitride semiconductor layer; and a third nitride semiconductor layer formed on the second nitride semiconductor layer. A region of the third nitride semiconductor layer located below the gate electrode is formed with a control region having a p-type conductivity, and a region of the third nitride semiconductor layer located between the gate electrode and each of the source electrode and the drain electrode is formed with a high resistive region having a higher resistance than the that of the control region.

    摘要翻译： 氮化物半导体器件包括：第一氮化物半导体层; 形成在所述第一氮化物半导体层上并且具有比所述第一氮化物半导体层更宽的带隙的第二氮化物半导体层; 以及形成在所述第二氮化物半导体层上的第三氮化物半导体层。 位于栅电极下方的第三氮化物半导体层的区域形成有具有p型导电性的控制区域，以及位于栅电极与源电极和漏极之间的第三氮化物半导体层的区域 形成有具有比控制区域更高的电阻的高电阻区域。

    NITRIDE SEMICONDUCTOR DEVICE
    95.
    发明申请
    NITRIDE SEMICONDUCTOR DEVICE 审中-公开
    氮化物半导体器件

    公开(公告)号：US20100327320A1

    公开(公告)日：2010-12-30

    申请号：US12879565

    申请日：2010-09-10

    申请人： Hiroaki Ueno ,  Manabu Yanagihara ,  Tetsuzo Ueda ,  Yasuhiro Uemoto ,  Tsuyoshi Tanaka ,  Daisuke Ueda

    发明人： Hiroaki Ueno ,  Manabu Yanagihara ,  Tetsuzo Ueda ,  Yasuhiro Uemoto ,  Tsuyoshi Tanaka ,  Daisuke Ueda

    IPC分类号： H01L29/80

    CPC分类号： H01L29/7783 ,  H01L21/02381 ,  H01L21/0242 ,  H01L21/02458 ,  H01L21/02502 ,  H01L21/0254 ,  H01L29/1066 ,  H01L29/2003 ,  H01L29/4175 ,  H01L29/432 ,  H01L29/452 ,  H01L29/7787

    摘要： A nitride semiconductor device includes: a first semiconductor layer made of first nitride semiconductor; a second semiconductor layer formed on a principal surface of the first semiconductor layer and made of second nitride semiconductor having a bandgap wider than that of the first nitride semiconductor; a control layer selectively formed on, or above, an upper portion of the second semiconductor layer and made of third nitride semiconductor having a p-type conductivity; source and drain electrodes formed on the second semiconductor layer at respective sides of the control layer; a gate electrode formed on the control layer; and a fourth semiconductor layer formed on a surface of the first semiconductor layer opposite to the principal surface, having a potential barrier in a valence band with respect to the first nitride semiconductor and made of fourth nitride semiconductor containing aluminum.

    摘要翻译： 氮化物半导体器件包括：由第一氮化物半导体制成的第一半导体层; 第二半导体层，其形成在第一半导体层的主表面上并且由具有比第一氮化物半导体的带隙宽的第二氮化物半导体构成; 选择性地形成在所述第二半导体层的上部并且由上述第二半导体层的上部制成的具有p型导电性的第三氮化物半导体的控制层; 源极和漏极，形成在控制层的相应侧上的第二半导体层上; 形成在所述控制层上的栅电极; 以及形成在与所述主表面相对的所述第一半导体层的表面上的第四半导体层，所述第四半导体层相对于所述第一氮化物半导体具有价带中的势垒，并且由包含铝的第四氮化物半导体制成。

    PLASMA DISPLAY PANEL DRIVING DEVICE AND PLASMA DISPLAY
    96.
    发明申请
    PLASMA DISPLAY PANEL DRIVING DEVICE AND PLASMA DISPLAY 审中-公开
    等离子显示面板驱动装置和等离子显示器

    公开(公告)号：US20100321363A1

    公开(公告)日：2010-12-23

    申请号：US12518005

    申请日：2008-06-19

    申请人： Tatsuo Morita ,  Manabu Yanagihara ,  Hidetoshi Ishida ,  Yasuhiro Uemoto ,  Manabu Inoue

    发明人： Tatsuo Morita ,  Manabu Yanagihara ,  Hidetoshi Ishida ,  Yasuhiro Uemoto ,  Manabu Inoue

    IPC分类号： G09G3/28

    CPC分类号： G09G3/294 ,  G09G3/2965

    摘要： A plasma display panel driving device includes an electrode driving unit for generating a drive pulse to be applied to an electrode of a plasma display panel. The electrode driving unit has a plurality of switches. At least one of the plurality of switches is a switch device including a dual-gate semiconductor device. The dual-gate semiconductor device 10 has a semiconductor multilayer 13 formed on a substrate 11 and made of a nitride semiconductor or a silicon carbide semiconductor, a source electrode 16 and a drain electrode 17 formed and spaced apart from each other on the semiconductor multilayer 13, and a first gate electrode 18A and a second gate electrode 18B formed between the source electrode 16 and the drain electrode 17, successively from the source electrode 16 side.

    摘要翻译： 等离子体显示面板驱动装置包括用于产生施加到等离子体显示面板的电极的驱动脉冲的电极驱动单元。 电极驱动单元具有多个开关。 多个开关中的至少一个是包括双栅极半导体器件的开关器件。 双栅极半导体器件10具有形成在基板11上并由氮化物半导体或碳化硅半导体形成的半导体层叠体13，在半导体层叠体13上形成并隔开的源电极16和漏电极17 以及从源极电极16侧依次形成在源极电极16和漏极电极17之间的第一栅极电极18A和第二栅极电极18B。

    High voltage SOI semiconductor device
    97.
    再颁专利
    High voltage SOI semiconductor device 有权
    高电压SOI半导体器件

    公开(公告)号：USRE41368E1

    公开(公告)日：2010-06-08

    申请号：US11076585

    申请日：2005-03-09

    申请人： Yasuhiro Uemoto ,  Katsushige Yamashita ,  Takashi Miura

    发明人： Yasuhiro Uemoto ,  Katsushige Yamashita ,  Takashi Miura

    IPC分类号： H01L31/0392

    CPC分类号： H01L29/7812 ,  H01L21/76286 ,  H01L29/0615 ,  H01L29/063 ,  H01L29/7394 ,  H01L29/7436 ,  H01L29/78 ,  H01L29/7824 ,  H01L29/7835 ,  H01L29/78606 ,  H01L29/78624 ,  H01L29/78654 ,  H01L29/8611

    摘要： In an SOI (Silicon On Insulator) semiconductor device, a first semiconductor layer overlies a semiconductor substrate so as to sandwich an insulating layer, and second and third semiconductor layers with a different conductivity type from the second semiconductor layer are formed on the surface of the first semiconductor layer. At the interface between the first semiconductor layer and the insulating layer, a fourth semiconductor layer with a different conductivity type from the first semiconductor layer is formed. The fourth semiconductor layer includes an impurity of larger than 3×1012/cm2 so as not to be completely depleted even though a reverse bias voltage is applied between the second and third semiconductor layers.

    摘要翻译： 在SOI（绝缘体上硅）半导体器件中，第一半导体层覆盖在半导体衬底上以夹住绝缘层，并且在第二半导体层的表面上形成具有与第二半导体层不同的导电类型的第二和第三半导体层 第一半导体层。 在第一半导体层和绝缘层之间的界面处，形成具有与第一半导体层不同的导电类型的第四半导体层。 第四半导体层包括大于3×10 12 / cm 2的杂质，即使在第二和第三半导体层之间施加反向偏置电压也不会完全耗尽。

    Semiconductor device
    100.
    发明申请
    Semiconductor device 审中-公开
    半导体器件

    公开(公告)号：US20070284653A1

    公开(公告)日：2007-12-13

    申请号：US11785801

    申请日：2007-04-20

    申请人： Hiroaki Ueno ,  Manabu Yanagihara ,  Yasuhiro Uemoto ,  Tsuyoshi Tanaka

    发明人： Hiroaki Ueno ,  Manabu Yanagihara ,  Yasuhiro Uemoto ,  Tsuyoshi Tanaka

    IPC分类号： H01L29/792

    CPC分类号： H01L29/7786 ,  H01L29/1066 ,  H01L29/2003 ,  H01L29/452

    摘要： A semiconductor device includes a first group III-V nitride semiconductor layer, a second group III-V nitride semiconductor layer having a larger band gap than the first group Ill-V nitride semiconductor layer and at least one ohmic electrode successively formed on a substrate. The ohmic electrode is formed so as to have a base portion penetrating the second group III-V nitride semiconductor layer and reaching a portion of the first group III-V nitride semiconductor layer disposed beneath a two-dimensional electron gas layer. An impurity doped layer is formed in portions of the first group III-V nitride semiconductor layer and the second group III-V nitride semiconductor layer in contact with the ohmic electrode.

    摘要翻译： 半导体器件包括第一III-V族氮化物半导体层，具有比第一组III-V族氮化物半导体层更大的带隙的第二III-V族氮化物半导体层和在衬底上依次形成的至少一个欧姆电极。 欧姆电极形成为具有穿透第二III-V族氮化物半导体层并且到达设置在二维电子气体层下方的第一III-V族氮化物半导体层的一部分的基极部分。 在与欧姆电极接触的第一III-V族氮化物半导体层和第二III-V族氮化物半导体层的部分中形成杂质掺杂层。