公开(公告)号：US10061527B2

公开(公告)日：2018-08-28

申请号：US15714710

申请日：2017-09-25

Applicant: Toshiba Memory Corporation

Inventor： Yoon Tze Chin ,  Norikazu Yoshida ,  Mitsuru Anazawa

IPC: G11C5/14 ,  G06F3/06 ,  G11C11/4074 ,  G11C16/30

CPC classification number: G06F3/0625 ,  G06F3/0634 ,  G06F3/0679 ,  G06F13/16 ,  G11C5/14 ,  G11C5/143 ,  G11C5/147 ,  G11C7/04 ,  G11C11/4074 ,  G11C16/30 ,  Y02D10/154

Abstract: A memory system includes non-volatile memory. The memory system includes a controller that controls data transfer between a host and the non-volatile memory, and a power supply unit that supplies a voltage to the controller. Further, the controller includes a power supply control unit that determines the voltage supplied to a module in the controller on the basis of an operation condition determined with the host. The power supply unit adjusts the voltage supplied to the module in accordance with a command from the power supply control unit.

公开(公告)号：US20180224916A1

公开(公告)日：2018-08-09

申请号：US15845259

申请日：2017-12-18

Applicant: L. Pierre de Rochemont

Inventor： L. Pierre de Rochemont

IPC: G06F1/32 ,  G06F15/80 ,  G06F1/28 ,  G06F9/30 ,  G06F9/38 ,  G06F12/0815 ,  G06F12/0862 ,  G06F12/0875 ,  H01L27/02 ,  H01L25/16 ,  H01L25/065 ,  H01L21/84 ,  H01L21/762 ,  H01L21/00 ,  G11C7/10 ,  G06F1/26 ,  G06F13/42 ,  G06F13/36 ,  G06F13/24 ,  G06F13/16 ,  G06F12/1009

CPC classification number: G06F1/3203 ,  G06F1/26 ,  G06F1/28 ,  G06F1/324 ,  G06F3/0619 ,  G06F3/0625 ,  G06F3/065 ,  G06F3/0685 ,  G06F9/3001 ,  G06F9/30043 ,  G06F9/30098 ,  G06F9/3802 ,  G06F12/0815 ,  G06F12/0862 ,  G06F12/0875 ,  G06F12/1009 ,  G06F13/1605 ,  G06F13/1673 ,  G06F13/1689 ,  G06F13/24 ,  G06F13/36 ,  G06F13/42 ,  G06F15/80 ,  G06F2212/1024 ,  G06F2212/452 ,  G06F2212/602 ,  G06F2212/621 ,  G06F2212/65 ,  G06F2213/0038 ,  G11C7/1072 ,  H01L21/00 ,  H01L21/76229 ,  H01L21/84 ,  H01L25/0652 ,  H01L25/16 ,  H01L27/0207 ,  H01L2924/0002 ,  H01L2924/14 ,  H01L2924/3011 ,  Y02D10/14 ,  Y02D10/151 ,  Y10S257/00 ,  H01L2924/00

Abstract: A hybrid system-on-chip provides a plurality of memory and processor die mounted on a semiconductor carrier chip that contains a fully integrated power management system that switches DC power at speeds that match or approach processor core clock speeds, thereby allowing the efficient transfer of data between off-chip physical memory and processor die.

公开(公告)号：US20180203643A1

公开(公告)日：2018-07-19

申请号：US15743330

申请日：2016-08-16

Applicant: Adesto Technologies Corporation

Inventor： Bard M. Pedersen

IPC: G06F3/06 ,  G11C5/14

CPC classification number: G06F3/0659 ,  G06F3/0604 ,  G06F3/0625 ,  G06F3/0634 ,  G06F3/0679 ,  G11C5/148

Abstract: A method of controlling an ultra-deep power down (UDPD) mode in a memory device, can include: receiving a write command from a host via an interface; beginning a write operation on the memory device to execute the write command; reading an auto-UDPD (AUDPD) configuration bit from a status register; switching the interface to a Single SPI mode in response to the write command and the AUDPD configuration bit being set; completing the write operation on the memory device; automatically entering the UDPD mode upon completion of the write operation in response to the AUDPD configuration bit being set; and entering a standby mode upon completion of the write operation in response to the AUDPD configuration bit being cleared.

公开(公告)号：US20180203628A1

公开(公告)日：2018-07-19

申请号：US15812377

申请日：2015-06-30

Applicant: EMC IP Holding Company LLC

Inventor： Roman Sergeevich Oderov ,  Alexander Nikolaevich Alexeev ,  Rustem Valeryevich Rafikov

IPC: G06F3/06

CPC classification number: G06F3/0625 ,  G06F3/0629 ,  G06F3/0653 ,  G06F3/0655 ,  G06F3/067 ,  Y02D10/154

Abstract: There is disclosed herein techniques for use in energy-efficient certification of data storage systems. In one embodiment, the techniques comprise a method including a number of steps. The method comprises providing instructions to perform operations in connection with a data storage system, wherein the instructions comprise a set of data storage configuration parameters. The method also comprises receiving results in connection with performed operations, wherein the results comprise power consumed and performance of the data storage system. The method further comprises determining an optimum energy efficient data storage configuration based on the results. The optimum energy efficient data storage configuration is dependent on the power consumed and the performance of the data storage system.

公开(公告)号：US20180189183A1

公开(公告)日：2018-07-05

申请号：US15906938

申请日：2018-02-27

Applicant: Western Digital Technologies, Inc.

Inventor： Scott E. Burton ,  Kenny T. Coker ,  Robert M. Fallone

IPC: G06F12/0866 ,  G06F3/06

CPC classification number: G06F12/0866 ,  G06F3/061 ,  G06F3/0611 ,  G06F3/0613 ,  G06F3/0625 ,  G06F3/0629 ,  G06F3/0634 ,  G06F3/0659 ,  G06F3/0673 ,  G06F3/0674 ,  G06F3/0679 ,  G06F11/3034 ,  G06F11/3055 ,  G06F11/3058 ,  Y02D10/154

Abstract: A disk drive is disclosed comprising a head actuated over a disk comprising a plurality of tracks, wherein each track comprises a plurality of data sectors comprising a disk block size. A host write command is received comprising data blocks having a host block size less than the disk block size. A misalignment is detected between the data blocks and the disk block size, and when the misalignment is detected, at least one of the data blocks is stored in a write cache. A command rate limit is adjusted as a function of the write cache, wherein the command rate limit defines a limit on a number of commands received from a host.

公开(公告)号：US10013195B2

公开(公告)日：2018-07-03

申请号：US15162748

申请日：2016-05-24

Applicant: SK hynix Inc.

Inventor： Do Yun Lee ,  Min Chang Kim ,  Chang Hyun Kim ,  Jae Jin Lee ,  Hun Sam Jung

IPC: G11C5/02 ,  G06F3/06 ,  G06F13/28

CPC classification number: G06F3/0625 ,  G06F3/0604 ,  G06F3/0689 ,  G06F13/287 ,  Y02D10/14

Abstract: A memory module may include a plurality of memory groups configured to include a plurality of memory packages, respectively, and input/output data through input/output pins. The memory module may include a control circuit configured to activate one or more of the plurality of memory groups on a basis of an address signal. The memory module may include a multiplexer circuit configured to couple the memory group activated on the basis of the address signal to input/output buses of the memory module.

公开(公告)号：US20180181186A1

公开(公告)日：2018-06-28

申请号：US15391195

申请日：2016-12-27

Applicant: Paul S. DIEFENBAUGH ,  Kristoffer D. FLEMING

Inventor： Paul S. DIEFENBAUGH ,  Kristoffer D. FLEMING

IPC: G06F1/32 ,  G06F3/06

CPC classification number: G06F3/067 ,  G06F1/3275 ,  G06F3/0625 ,  G06F3/0634 ,  G06F3/0656 ,  G06F3/0689

Abstract: A method and apparatus for buffering data to enable longer reduced power consumption state residency are described. In one embodiment, a computing system comprises a first device operable in one or more reduced power consumption states and a non-reduced power consumption state; one or more I/O devices operable to generate data to be forwarded to the first device; and a write buffer coupled to the first device and the one or more I/O devices to temporarily store data received from one or more I/O devices when the first device is in one of the one or more reduced power consumption states.

公开(公告)号：US10001938B2

公开(公告)日：2018-06-19

申请号：US14990453

申请日：2016-01-07

Applicant: Dell Products L.P.

Inventor： Kanaka Charyulu B ,  Deepu Syam Sreedhar M ,  Sandeep Agarwal ,  Gary E. Billingsley ,  Abhijit Rajkumar Khande

IPC: G06F12/00 ,  G06F3/06

CPC classification number: G06F3/0625 ,  G06F3/0613 ,  G06F3/0665 ,  G06F3/0689 ,  Y02D10/154

Abstract: In accordance with embodiments of the present disclosure, a method may include receiving requirements for building a virtual storage resource from an array of physical storage resources, receiving performance metrics and power metrics of the physical storage resources of the array available for inclusion in the virtual storage resource, determining a plurality of unique combinations of the available physical storage resources that could be used to build the virtual storage resource, determining an effective performance, an effective performance penalty, a total power consumption, and an effective power penalty for each of the plurality of unique combinations, and selecting a single combination of the plurality of unique combinations for the virtual storage resource based on effective performances, effective performance penalties, total power consumptions, and effective power penalties of the plurality of unique combinations.

公开(公告)号：US20180157417A1

公开(公告)日：2018-06-07

申请号：US15820727

申请日：2017-11-22

Applicant: Silicon Motion, Inc.

Inventor： Fu-Jen SHIH ,  Yen-Hung CHEN

IPC: G06F3/06 ,  G06F9/44

CPC classification number: G06F3/061 ,  G06F3/0625 ,  G06F3/0634 ,  G06F3/0679 ,  G06F9/4405 ,  G06F13/42

Abstract: A host device coupled to a data storage device via a predetermined interface includes a processor and a signal processing device. The processor accesses data stored in the data storage device via the predetermined interface. The signal processing device performs signal processing on the data. The processor transmits a first power mode change request packet to the data storage device via the predetermined interface, to request to change a data transfer speed of the predetermined interface from a first speed to a second speed. The processor receives a first power mode change confirm packet via the predetermined interface from the data storage device, and in response to the first power mode change confirm packet, the processor determines to keep the data transfer speed at the first speed and does not change the data transfer speed to the second speed.

公开(公告)号：US20180157309A1

公开(公告)日：2018-06-07

申请号：US15823328

申请日：2017-11-27

Applicant: Silicon Motion, Inc.

Inventor： Fu-Jen SHIH ,  Yen-Hung CHEN

IPC: G06F1/32 ,  G06F3/06

CPC classification number: G06F1/3275 ,  G06F1/3225 ,  G06F1/3253 ,  G06F1/3296 ,  G06F3/0625 ,  G06F3/0634 ,  G06F3/0653 ,  G06F3/0659 ,  G06F3/068 ,  G06F13/1673 ,  G06F13/28 ,  Y02D10/154

Abstract: A data storage device coupled to a host device via a predetermined interface includes a memory device, an SRAM, and a controller. The controller is coupled to the memory device and the SRAM. The controller receives a first power mode change request packet requesting to change the data transfer speed of the predetermined interface from a first speed to a second speed via the predetermined interface from the host device, and in response to the first power mode change request packet, the controller determines whether the operation status of the data storage device is busy. When the operation status of the data storage device is busy, the controller determines to reject the request to change the data transfer speed and keeps the data transfer speed at the first speed and does not change the data transfer speed to the second speed.