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    Semiconductor devices and methods of forming a barrier metal in semiconductor devices
    91.
    发明授权
    Semiconductor devices and methods of forming a barrier metal in semiconductor devices 失效
    在半导体器件中形成阻挡金属的半导体器件和方法

    公开(公告)号：US07186646B2

    公开(公告)日：2007-03-06

    申请号：US10925777

    申请日：2004-08-25

    申请人： Han-Choon Lee

    发明人： Han-Choon Lee

    IPC分类号： H01L21/44

    CPC分类号： H01L21/76843 ,  H01L21/28518 ,  H01L21/28562 ,  H01L21/76846 ,  H01L21/76855 ,  H01L21/76856 ,  H01L21/76862 ,  H01L23/5226 ,  H01L2924/0002 ,  H01L2924/00

    摘要： Semiconductor devices and methods of forming a barrier metal in semiconductor devices are disclosed. A disclosed semiconductor device includes a metal layer on a semiconductor substrate; an interlayer dielectric layer on the metal layer, a hole in the interlayer dielectric layer that exposes a portion of the metal layer; and a barrier metal on inner walls of the hole. The barrier metal is made of TaSiN having a resistivity less than or equal to about 10,000 μohm-cm.

    摘要翻译： 公开了在半导体器件中形成阻挡金属的半导体器件和方法。 所公开的半导体器件包括在半导体衬底上的金属层; 在所述金属层上的层间介质层，所述层间电介质层中露出所述金属层的一部分的孔; 和孔内壁上的阻挡金属。 阻挡金属由电阻率小于或等于约10,000欧姆 - 厘米的TaSiN制成。

    Method of depositing a metal seed layer on semiconductor substrates
    93.
    发明申请
    Method of depositing a metal seed layer on semiconductor substrates 有权
    在半导体衬底上沉积金属种子层的方法

    公开(公告)号：US20070020922A1

    公开(公告)日：2007-01-25

    申请号：US11450703

    申请日：2006-06-09

    申请人： Tony Chiang ,  Gongda Yao ,  Peijun Ding ,  Fusen Chen ,  Barry Chin ,  Gene Kohara ,  Zheng Xu ,  Hong Zhang

    发明人： Tony Chiang ,  Gongda Yao ,  Peijun Ding ,  Fusen Chen ,  Barry Chin ,  Gene Kohara ,  Zheng Xu ,  Hong Zhang

    IPC分类号： H01L21/4763

    CPC分类号： H01L21/76843 ,  C23C14/046 ,  C23C14/165 ,  H01L21/2855 ,  H01L21/76805 ,  H01L21/76844 ,  H01L21/76846 ,  H01L21/76862 ,  H01L21/76865 ,  H01L21/76871 ,  H01L21/76877 ,  H01L21/76879 ,  H01L21/76883

    摘要： We disclose a method of applying a sculptured layer of material on a semiconductor feature surface using ion deposition sputtering, wherein a surface onto which the sculptured layer is applied is protected to resist erosion and contamination by impacting ions of a depositing layer. A first protective layer of material is deposited on a substrate surface using traditional sputtering or ion deposition sputtering, in combination with sufficiently low substrate bias that a surface onto which the layer is applied is not eroded away or contaminated during deposition of the protective layer. Subsequently, a sculptured second layer of material is applied using ion deposition sputtering at an increased substrate bias, to sculpture a shape from a portion of the first protective layer of material and the second layer of depositing material. The method is particularly applicable to the sculpturing of barrier layers, wetting layers, and conductive layers upon semiconductor feature surfaces.

    摘要翻译： 我们公开了使用离子沉积溅射在半导体特征表面上施加雕刻的材料层的方法，其中施加有雕刻层的表面被保护以通过冲击沉积层的离子来抵抗侵蚀和污染。 使用传统的溅射或离子沉积溅射将第一保护层材料沉积在衬底表面上，结合足够低的衬底偏压，使得施加层的表面在保护层沉积期间不被腐蚀掉或被污染。 随后，使用离子沉积溅射在增加的衬底偏压下施加雕刻的第二材料层，以从材料的第一保护层的一部分和第二沉积材料层的一部分雕刻出形状。 该方法特别适用于在半导体特征表面上雕刻阻挡层，润湿层和导电层。

    GCIB processing of integrated circuit interconnect structures
    95.
    发明授权
    GCIB processing of integrated circuit interconnect structures 有权
    集成电路互连结构的GCIB处理

    公开(公告)号：US07115511B2

    公开(公告)日：2006-10-03

    申请号：US10701573

    申请日：2003-11-05

    申请人： John J. Hautala

    发明人： John J. Hautala

    IPC分类号： H01L21/302

    CPC分类号： H01L21/76865 ,  C23F4/00 ,  H01J2237/0812 ,  H01L21/32135 ,  H01L21/76843 ,  H01L21/76862 ,  H01L21/76877

    摘要： Method for removing and/or redistributing material in the trenches and/or vias of integrated circuit interconnect structures by a gas cluster ion beam (GCIB) is described to improve the fabrication process and quality of metal interconnects in an integrated circuit. The process entails opening up an undesired ‘necked in’ region at the entrance to the structure, re-depositing the barrier metal from thicker areas such as the neck or bottom of the structure to the side walls and/or removing some of the excess and undesired material on the bottom of the structure by sputtering. The GCIB process may be applied after the barrier metal deposition and before the copper seed layer/copper electroplating or the process may be applied after the formation of the copper seed layer and before electroplating. The method may extend the usability of the known interconnect deposition technologies to next generation integrated circuits and beyond.

    摘要翻译： 描述了通过气体簇离子束（GCIB）去除和/或重新分布集成电路互连结构的沟槽和/或通孔中的材料的方法，以改善集成电路中的金属互连的制造工艺和质量。 该过程需要在结构的入口处打开不期望的“颈缩”区域，将阻挡金属从诸如结构的颈部或底部的较厚区域重新沉积到侧壁和/或去除一些过量和 通过溅射在结构底部的不需要的材料。 可以在阻挡金属沉积之后并且在铜籽晶层/铜电镀之前以及在形成铜籽晶层之后和在电镀之前施加该方法之后应用GCIB工艺。 该方法可以将已知的互连沉积技术的可用性扩展到下一代集成电路及其以上。

    Method for forming a wiring of a semiconductor device, method for forming a metal layer of a semiconductor device and apparatus for performing the same
    96.
    发明授权
    Method for forming a wiring of a semiconductor device, method for forming a metal layer of a semiconductor device and apparatus for performing the same 有权
    用于形成半导体器件的布线的方法，用于形成半导体器件的金属层的方法及其执行方法

    公开(公告)号：US07105444B2

    公开(公告)日：2006-09-12

    申请号：US10857253

    申请日：2004-05-28

    申请人： Kyung-In Choi ,  Sang-Bom Kang ,  Seong-Geon Park ,  You-Kyoung Lee ,  Gil-Heyun Choi ,  Jong-Myeong Lee ,  Sang-Woo Lee

    发明人： Kyung-In Choi ,  Sang-Bom Kang ,  Seong-Geon Park ,  You-Kyoung Lee ,  Gil-Heyun Choi ,  Jong-Myeong Lee ,  Sang-Woo Lee

    IPC分类号： H01L21/44

    CPC分类号： H01L21/28556 ,  C23C16/34 ,  C23C16/45553 ,  H01L21/28562 ,  H01L21/76843 ,  H01L21/7685 ,  H01L21/76858 ,  H01L21/76862 ,  H01L21/76867 ,  H01L21/76877

    摘要： In a method for forming a wiring of a semiconductor device using an atomic layer deposition, an insulating interlayer is formed on a substrate. Tantalum amine derivatives represented by a chemical formula Ta(NR1)(NR2R3)3 in which R1, R2 and R3 represent H or C1–C6 alkyl group are introduced onto the insulating interlayer. A portion of the tantalum amine derivatives is chemisorbed on the insulating interlayer. The rest of tantalum amine derivatives non-chemisorbed on the insulating interlayer is removed from the insulating interlayer. A reacting gas is introduced onto the insulating interlayer. A ligand in the tantalum amine derivatives chemisorbed on the insulating interlayer is removed from the tantalum amine derivatives by a chemical reaction between the reacting gas and the ligand to form a solid material including tantalum nitride. The solid material is accumulated on the insulating interlayer through repeating the above processes to form a wiring.

    摘要翻译： 在使用原子层沉积形成半导体器件的布线的方法中，在基板上形成绝缘中间层。 由化学式Ta（NR 1）3（NR 2 R 3）3表示的钽胺衍生物，其中 R 1，R 2和R 3代表H或C 1 -C 6 >烷基引入到绝缘中间层上。 一部分钽胺衍生物被化学吸附在绝缘中间层上。 在绝缘中间层上除去非化学吸附在绝缘中间层上的其余的钽胺衍生物。 将反应气体引入到绝缘中间层上。 化学吸附在绝缘中间层上的钽胺衍生物中的配体通过反应气体和配位体之间的化学反应从钽胺衍生物中除去以形成包括氮化钽的固体材料。 通过重复上述处理，将固体材料积聚在绝缘层间，形成布线。

    Semiconductor device
    97.
    发明申请
    Semiconductor device 失效

    公开(公告)号：US20060154482A1

    公开(公告)日：2006-07-13

    申请号：US10543378

    申请日：2003-12-26

    申请人： Eiichi Kondoh ,  Vincent Vezin ,  Kenichi Kubo ,  Yoshinori Kureishi ,  Tomohiro Ohta

    发明人： Eiichi Kondoh ,  Vincent Vezin ,  Kenichi Kubo ,  Yoshinori Kureishi ,  Tomohiro Ohta

    IPC分类号： H01L21/44

    CPC分类号： H01L21/76843 ,  H01L21/28556 ,  H01L21/76862

    摘要： An object of the invention is to make it possible to perform the embedding of a Cu diffusion preventing film and a Cu film to a fine pattern of a high aspect ratio by using a medium of a supercritical state in a manufacturing process of a semiconductor device. The object of the invention is achieved by a substrate processing method comprising a first step of processing a substrate by supplying a first processing medium containing a first medium of a supercritical state onto the substrate, a second step of forming a Cu diffusion preventing film on the substrate by supplying a second processing medium containing a second medium of a supercritical state onto the substrate, and a third step of forming a Cu film on the substrate by supplying a third processing medium containing a third medium of a supercritical state onto the substrate.

    Method for forming metal silicide layer in active area of semiconductor device
    99.
    发明授权
    Method for forming metal silicide layer in active area of semiconductor device 失效
    在半导体器件有源区中形成金属硅化物层的方法

    公开(公告)号：US07060577B2

    公开(公告)日：2006-06-13

    申请号：US10613331

    申请日：2003-07-03

    申请人： In-Haeng Lee ,  Yoon-Jik Lee

    发明人： In-Haeng Lee ,  Yoon-Jik Lee

    IPC分类号： H01L21/336

    CPC分类号： H01L21/76843 ,  H01L21/28518 ,  H01L21/321 ,  H01L21/76855 ,  H01L21/76862 ,  H01L29/665

    摘要： The present invention provides a method for forming a metal silicide layer in an active area of the semiconductor device. The method for forming the metal silicide layer includes: forming a source/drain junction area on a silicon substrate; forming an attack protection layer on the source/drain junction area, wherein the attack protection layer is electrically conductive and prevents a silicon substrate attack caused by chlorine (Cl) gas; forming a titanium (Ti) layer over the attack protection layer through a low pressure chemical vapor deposition (LPCVD) process using a source gas of TiCl4; and diffusing the Ti layer into the attack protection layer to thereby form a metal silicide layer.

    摘要翻译： 本发明提供了在半导体器件的有源区域中形成金属硅化物层的方法。 形成金属硅化物层的方法包括：在硅衬底上形成源极/漏极结区域; 在源极/漏极结区域上形成攻击保护层，其中攻击保护层是导电的并且防止由氯（Cl）气体引起的硅衬底攻击; 通过使用TiCl 4的源气体的低压化学气相沉积（LPCVD）工艺在侵蚀保护层上形成钛（Ti）层; 并将Ti层扩散到攻击保护层中，从而形成金属硅化物层。