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公开(公告)号：US20240128146A1
公开(公告)日：2024-04-18
申请号：US18474250
申请日：2023-09-26
发明人： HO-MING TONG , CHAO-CHUN LU
IPC分类号： H01L23/367 , H01L23/00 , H01L23/528 , H01L25/065 , H10B80/00
CPC分类号： H01L23/3672 , H01L23/5286 , H01L24/08 , H01L25/0652 , H10B80/00 , H01L2224/08225
摘要： The present application discloses a semiconductor package which includes a processor die powered by either a front-side or a backside power delivery network, a plurality of memory dies and control dies stacked over the processor die, a plurality of high-thermal-conductivity (HTC) interconnects formed on, located between and/or placed side-by-side with the dies, a HTC substrate carrying all the dies, a HTC structural member, and a HTC heat spreader/heatsink with the dies and the HTC heat spreader thermally coupled to other HTC components in the semiconductor package. The semiconductor components can be configured to go beyond the traditional single-sided interconnection and cooling topologies to enable dual-or multi-sided cooling, power supply, and signaling.
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公开(公告)号：US20240105689A1
公开(公告)日：2024-03-28
申请号：US18212514
申请日：2023-06-21
发明人： Seokhyun Lee
IPC分类号： H01L25/10 , H01L23/00 , H01L23/498 , H01L25/00 , H10B80/00
CPC分类号： H01L25/105 , H01L23/49816 , H01L23/49822 , H01L23/49833 , H01L23/49838 , H01L24/08 , H01L24/16 , H01L24/32 , H01L24/73 , H01L25/50 , H10B80/00 , H01L2224/08225 , H01L2224/16145 , H01L2224/16227 , H01L2224/32145 , H01L2224/32225 , H01L2224/73204 , H01L2225/1023 , H01L2225/1041 , H01L2225/1058 , H01L2924/1431 , H01L2924/1436
摘要： A semiconductor package includes: a lower redistribution wiring layer having: a first chip mounting region; a peripheral region, and lower redistribution wirings; a logic semiconductor chip mounted in the first chip mounting region, the logic semiconductor chip having a plurality of first through electrodes that are electrically connected to at least some of the lower redistribution wirings; a first sealing member covering the logic semiconductor chip, a plurality of conductive connectors penetrating the first sealing member in the peripheral region; an upper redistribution wiring layer provided on the first seal and having upper redistribution wirings that are electrically connected to the plurality of conductive connectors, the upper redistribution wiring layer having at least one second chip mounting region that overlaps at least a portion of the first chip mounting region; and at least one memory semiconductor chip mounted in the second chip mounting region using first and second conductive bumps.
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公开(公告)号：US20240088002A1
公开(公告)日：2024-03-14
申请号：US18244315
申请日：2023-09-11
发明人： Yenheng CHEN , Chengchung LIN
IPC分类号： H01L23/498 , H01L21/48 , H01L21/56 , H01L21/683 , H01L23/00 , H01L23/29 , H01L25/065
CPC分类号： H01L23/49822 , H01L21/4853 , H01L21/4857 , H01L21/568 , H01L21/6835 , H01L23/293 , H01L23/49811 , H01L23/49838 , H01L23/49894 , H01L24/03 , H01L24/08 , H01L24/80 , H01L25/0655 , H01L2221/68359 , H01L2221/68372 , H01L2221/68381 , H01L2224/03916 , H01L2224/08225 , H01L2224/80895 , H01L2224/80896 , H01L2924/15174 , H01L2924/3511 , H01L2924/3512 , H01L2924/381
摘要： A system-level fan-out packaging structure and a method for manufacturing the same are disclosed. The method includes: forming a rewiring layer on a supporting substrate, the rewiring layer having a first surface and a second surface opposite to the first surface, wherein the rewiring layer includes at least one inorganic dielectric layer and at least one metal wiring layer; forming a hybrid bonding structure between the first surface of the rewiring layer and semiconductor chips to electrically couple them, wherein the hybrid bonding structure includes a first bonding layer formed on the first surface of the rewiring layer; a plastic packaging layer on the first surface of the rewiring layer to cover the semiconductor chips; removing the supporting substrate to expose the second surface of the rewiring layer; and providing a packaging substrate electrically coupled to the second surface of the rewiring layer.
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公开(公告)号：US11903298B2
公开(公告)日：2024-02-13
申请号：US17259373
申请日：2020-03-27
发明人： Junbo Wei , Shengji Yang , Kuanta Huang , Pengcheng Lu , Yuanlan Tian
IPC分类号： H01L27/32 , H10K59/88 , H10K59/131 , H10K71/70 , H10K59/80 , H01L21/66 , H10K50/88 , H10K77/10 , H01L23/00 , H10K71/00 , H10K102/00
CPC分类号： H10K59/88 , H01L22/30 , H01L22/32 , H10K50/88 , H10K59/131 , H10K59/873 , H10K71/70 , H10K77/111 , H01L24/05 , H01L24/08 , H01L2224/05556 , H01L2224/05564 , H01L2224/05573 , H01L2224/08225 , H10K59/8731 , H10K71/851 , H10K2102/351
摘要： A display panel includes a driving backplane, a plurality of detection pads, a light emitting function layer, and a flexible circuit board. The driving backplane has a pixel driving region and a peripheral region, and the peripheral region has bonding pads; an edge of the driving backplane is surrounded by a first section and a second section, and the bonding pads are located between the first section and the pixel driving region; a plurality of detection pads are disposed in and distributed along the second section; a light emitting function layer is disposed on the driving backplane and located in the pixel driving region; a flexible circuit board extends between the first section and the pixel driving region, and is bonded to the bonding pads; a first packaging layer is disposed on the light emitting function layer.
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公开(公告)号：US20240047471A1
公开(公告)日：2024-02-08
申请号：US17765831
申请日：2021-11-11
发明人： Can HUANG , Wenxu XIANYU , Chunpeng ZHANG , Tiyao MA
IPC分类号： H01L27/12 , H10K59/131 , H10K59/90 , H01L23/00
CPC分类号： H01L27/124 , H10K59/131 , H10K59/90 , H01L24/08 , H01L24/05 , H01L2224/08225 , H01L2224/05624 , H01L2224/0557
摘要： A display panel and a display device are provided. The display panel includes a driving backplane and a plurality of display components arranged in an array and on the driving backplane, and each of the display components comprises a plurality of first bonding terminals and a plurality of signal lines, and each of the display components is electrically connected to the driving backplane through the plurality of first bonding terminals, and each of the signal lines is electrically connected to the corresponding first bonding terminal, respectively, to alleviate the technical problem that relatively larger splicing gaps exist at the splicing sites of the current super-large display screen.
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公开(公告)号：US20240047338A1
公开(公告)日：2024-02-08
申请号：US18151261
申请日：2023-01-06
发明人： Ming-Fa Chen , Yun-Han Lee , Lee-Chung Lu
IPC分类号： H01L23/498 , H01L25/065 , H01L23/538 , H01L23/42 , H01L21/48 , H01L25/00 , H01L23/00
CPC分类号： H01L23/49844 , H01L25/0655 , H01L23/5383 , H01L23/42 , H01L21/4857 , H01L25/50 , H01L24/08 , H01L24/80 , H01L2224/08225 , H01L2224/80895 , H01L2224/80896
摘要： In an embodiment, a device includes: a first integrated circuit die including a first device layer and a first front-side interconnect structure, the first front-side interconnect structure including first interconnects interconnecting first devices of the first device layer; a second integrated circuit die including a second device layer and a second front-side interconnect structure, the second front-side interconnect structure including second interconnects interconnecting second devices of the second device layer; and an interposer bonded to a back-side of the first integrated circuit die and to a back-side of the second integrated circuit die, the interposer including a die-to-die interconnect structure, the die-to-die interconnect structure including a pillar, the first integrated circuit die overlapping the pillar.
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公开(公告)号：US20240032310A1
公开(公告)日：2024-01-25
申请号：US18163378
申请日：2023-02-02
发明人： Kyungdon MUN
IPC分类号： H10B80/00 , H01L23/538 , H01L23/00
CPC分类号： H10B80/00 , H01L23/5385 , H01L24/05 , H01L24/06 , H01L24/08 , H01L2224/0557 , H01L2224/06181 , H01L2224/08145 , H01L2224/08225 , H01L24/16 , H01L2224/16227 , H01L24/32 , H01L2224/32225 , H01L24/73 , H01L2224/73204 , H01L2224/73253 , H01L24/33 , H01L2224/33181 , H01L24/17 , H01L2224/17181 , H01L2924/1431 , H01L2924/14361 , H01L2924/14511 , H01L2924/1443 , H01L2924/1441 , H01L2924/1437 , H01L2924/1432
摘要： A semiconductor package may include a base wiring structure, a first bridge chip and a cache memory chip on the base wiring structure and spaced apart from each other in a horizontal direction, and logic semiconductor chips adjacent to each other on the first bridge chip and the cache memory chip. Logic semiconductor chips each may include a cache memory. The first bridge chip may overlap at least two of the logic semiconductor chips in a vertical direction and the first bridge chip may include first bridge wirings electrically connecting at least two of the logic semiconductor chips. The cache memory chip may overlap the cache memory of at least one of the logic semiconductor chips in the vertical direction and the cache memory chip may be electrically connected to the cache memory of at least one of the logic semiconductor chips.
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公开(公告)号：US20240021559A1
公开(公告)日：2024-01-18
申请号：US18252490
申请日：2021-02-25
发明人： Di ZHAN , Tianjian LIU , Tian ZENG , Wanli GUO
IPC分类号： H01L23/00 , H01L23/544 , H01L25/065 , H01L25/00
CPC分类号： H01L24/19 , H01L24/08 , H01L23/544 , H01L24/20 , H01L24/80 , H01L24/95 , H01L24/94 , H01L24/92 , H01L24/83 , H01L24/82 , H01L24/24 , H01L25/0652 , H01L25/50 , H01L2224/08145 , H01L2224/19 , H01L2224/211 , H01L2224/08225 , H01L2224/80896 , H01L2224/80357 , H01L2224/95 , H01L2224/94 , H01L2224/92244 , H01L2224/8313 , H01L2224/821 , H01L2224/32145 , H01L2224/24145 , H01L2224/24147 , H01L2223/54426
摘要： A method of bonding first die(s) to a wafer and a die-stack structure includes: providing a first layer of first die(s), each of the first die(s) including a first metal layer; providing the wafer, which includes a second metal layer; bonding the first die(s) to the wafer; forming an insulating layer and a hole, the insulating layer covering the wafer around the first die(s) or filling gap(s) between the first die(s), the hole formed in the insulating layer around the first die(s); forming an interconnect structure in the hole, the first metal layer, the second metal layer and the interconnect structure are electrically connected, thus establishing electrical connection between the first die(s) and the wafer. In this method, it is unnecessary to form TSV within the first die(s), reducing difficulties in the design of internal wiring within the first die(s) and resulting in area savings of the first die(s).
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公开(公告)号：US20240021549A1
公开(公告)日：2024-01-18
申请号：US17866209
申请日：2022-07-15
发明人： Chih CHEN , Hsiang-Hou TSENG
IPC分类号： H01L23/00 , H01L25/00 , H01L25/065 , H01L21/48 , H01L23/498
CPC分类号： H01L24/05 , H01L24/03 , H01L24/08 , H01L24/80 , H01L25/50 , H01L25/0657 , H01L25/0652 , H01L25/0655 , H01L21/486 , H01L23/49827 , H01L2224/03462 , H01L2224/03464 , H01L2224/05639 , H01L2224/80203 , H01L2224/80092 , H01L2224/05147 , H01L2224/05083 , H01L2224/05573 , H01L2224/05166 , H01L2224/05181 , H01L2224/05186 , H01L2924/04941 , H01L2924/04953 , H01L2224/05026 , H01L2224/94 , H01L24/94 , H01L2224/08145 , H01L2224/08225 , H01L2224/80439 , H01L2224/97 , H01L21/561
摘要： A method includes forming a first connector and a second connector over a first wafer and a second wafer, respectively, in which each of the first and second connectors are formed by forming an opening in a dielectric layer; depositing a first metal layer in the opening, in which the first metal layer has a nano-twinned structure with (111) orientation; and depositing a second metal layer over the first metal layer, the second metal layer and the first metal layer being made of different materials, in which the second metal layer has a nano-twinned structure with (111) orientation; attaching the first wafer to the second wafer, such that that the second metal layer of the first connector on the first wafer is in contact with the second metal layer of the second connector on the second wafer; and performing a thermo-compression process to bond the first and second wafers.
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公开(公告)号：US11854992B2
公开(公告)日：2023-12-26
申请号：US17530868
申请日：2021-11-19
发明人： Chen-Hua Yu , Kai-Chiang Wu , Chun-Lin Lu
IPC分类号： H01L23/538 , H01L23/00 , H01L21/56 , H01L23/31 , H01L25/065 , H01L25/00
CPC分类号： H01L23/5389 , H01L21/565 , H01L21/566 , H01L23/3114 , H01L23/3128 , H01L23/3135 , H01L23/5383 , H01L23/5384 , H01L23/5386 , H01L24/19 , H01L24/20 , H01L25/0652 , H01L25/50 , H01L21/568 , H01L2224/04105 , H01L2224/08225 , H01L2224/12105 , H01L2224/16227 , H01L2224/73204 , H01L2224/73267 , H01L2224/80006 , H01L2924/15192
摘要： A method of manufacturing a semiconductor structure includes following operations. A first die is provided. A first molding is formed to encapsulate the first die. A second die is disposed over the first molding. A mold chase is disposed over the second die and the first molding. The mold chase includes a protrusion protruded from the mold chase towards the first molding. A molding material is disposed between the mold chase and the first molding. A second molding is formed to surround the second die. The second die is at least partially covered by the second molding. The disposing of the mold chase includes surrounding the protrusion of the mold chase by the molding material.
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