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公开(公告)号：US20240128146A1
公开(公告)日：2024-04-18
申请号：US18474250
申请日：2023-09-26
发明人： HO-MING TONG , CHAO-CHUN LU
IPC分类号： H01L23/367 , H01L23/00 , H01L23/528 , H01L25/065 , H10B80/00
CPC分类号： H01L23/3672 , H01L23/5286 , H01L24/08 , H01L25/0652 , H10B80/00 , H01L2224/08225
摘要： The present application discloses a semiconductor package which includes a processor die powered by either a front-side or a backside power delivery network, a plurality of memory dies and control dies stacked over the processor die, a plurality of high-thermal-conductivity (HTC) interconnects formed on, located between and/or placed side-by-side with the dies, a HTC substrate carrying all the dies, a HTC structural member, and a HTC heat spreader/heatsink with the dies and the HTC heat spreader thermally coupled to other HTC components in the semiconductor package. The semiconductor components can be configured to go beyond the traditional single-sided interconnection and cooling topologies to enable dual-or multi-sided cooling, power supply, and signaling.
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公开(公告)号：US20240006301A1
公开(公告)日：2024-01-04
申请号：US18345611
申请日：2023-06-30
发明人： HO-MING TONG , CHAO-CHUN LU
IPC分类号： H01L23/498 , H01L23/00 , H01L21/48 , H01L25/10
CPC分类号： H01L23/49894 , H01L23/49827 , H01L24/05 , H01L24/08 , H01L24/80 , H01L21/486 , H01L23/49838 , H01L25/105 , H01L2224/05647 , H01L2224/05571 , H01L2224/05573 , H01L2224/08237 , H01L2224/80896 , H01L2224/80357 , H01L2224/80379 , H01L2224/80486 , H01L2924/05442 , H01L2924/05042 , H01L2224/80447 , H01L2224/80012 , H01L24/16 , H01L2224/16227 , H01L2224/08145 , H01L23/481
摘要： A semiconductor package is provided. The semiconductor package includes an integrated circuit (IC) block and a first substrate. The IC block has a first interconnect layer. The first substrate carries the IC block. The first substrate includes a second interconnect layer facing the first interconnect layer and a third interconnect layer opposite to the second interconnect layer. Furthermore, at least one of the second interconnect layer or the third interconnect layer is composed of a dielectric material and a conductive material substantially identical to a corresponding dielectric material and a corresponding conductive material of the first interconnect layer.
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公开(公告)号：US20240234354A1
公开(公告)日：2024-07-11
申请号：US18542032
申请日：2023-12-15
发明人： HO-MING TONG , WEI YEN , CHAO-CHUN LU
CPC分类号： H01L24/08 , H01L24/05 , H01L24/80 , H01L25/167 , H01L2224/05124 , H01L2224/05139 , H01L2224/05144 , H01L2224/05147 , H01L2224/05155 , H01L2224/05157 , H01L2224/05163 , H01L2224/05164 , H01L2224/05166 , H01L2224/05169 , H01L2224/05172 , H01L2224/05173 , H01L2224/05176 , H01L2224/05178 , H01L2224/0518 , H01L2224/05181 , H01L2224/05184 , H01L2224/05609 , H01L2224/05611 , H01L2224/05613 , H01L2224/05616 , H01L2224/05618 , H01L2224/05624 , H01L2224/05639 , H01L2224/05644 , H01L2224/05647 , H01L2224/05663 , H01L2224/08145 , H01L2224/80224 , H01L2224/80895 , H01L2224/80896
摘要： A semiconductor package is provided. The semiconductor package includes a first die having a plurality of first metal pads at a first bonding side and a second die over the first die, having a plurality of second metal pads at a second bonding side facing the first bonding side. Each of the first metal pads corresponds to each of the second metal pads with a pitch no greater than about 10 μm. The semiconductor package further includes a first dielectric layer surrounding and in contact with a sidewall of the first metal pads and a second dielectric layer surrounding and in contact with a sidewall of the second metal pads. A method for manufacturing a semiconductor package is also provided.
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4.发明公开公开(公告)号：US20240128208A1
公开(公告)日：2024-04-18
申请号：US18471670
申请日：2023-09-21
发明人： HO-MING TONG , CHAO-CHUN LU
IPC分类号： H01L23/00 , H01L21/683 , H01L23/538 , H01L25/00 , H01L25/065 , H01L25/18
CPC分类号： H01L24/02 , H01L21/6835 , H01L23/5387 , H01L24/16 , H01L24/19 , H01L24/20 , H01L24/24 , H01L24/25 , H01L24/32 , H01L24/73 , H01L24/82 , H01L25/0652 , H01L25/0657 , H01L25/18 , H01L25/50 , H01L24/96 , H01L2221/68372 , H01L2224/0231 , H01L2224/02371 , H01L2224/02372 , H01L2224/16225 , H01L2224/19 , H01L2224/211 , H01L2224/221 , H01L2224/24137 , H01L2224/2518 , H01L2224/32145 , H01L2224/73217 , H01L2224/73259 , H01L2224/73267 , H01L2224/82005 , H01L2224/95001 , H01L2224/96 , H01L2225/06524 , H01L2225/06541 , H01L2225/06551
摘要： A semiconductor package includes a first integrated circuit (IC) structure. The first IC structure includes: a first body having a first primary surface and a first secondary surface, the first primary surface being substantially perpendicular to the first secondary surface; and an interconnect structure. The interconnect structure includes a primary redistribution layer (RDL) over the first primary surface, the primary RDL having a second secondary surface that is aligned with the first secondary surface of the first body, wherein the first secondary surface and the second secondary surface jointly form a secondary plane. The primary RDL further comprises a first conductive element exposed through the second secondary surface of the primary RDL; and a secondary RDL over the secondary plane, wherein the secondary RDL is electrically connected to the first conductive element of the primary RDL and other conductive elements of the first body exposed through the first secondary plane.
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公开(公告)号：US20240128150A1
公开(公告)日：2024-04-18
申请号：US18473999
申请日：2023-09-25
发明人： HO-MING TONG , CHAO-CHUN LU
IPC分类号： H01L23/367 , H01L23/00 , H01L23/498 , H01L25/065
CPC分类号： H01L23/3675 , H01L23/49822 , H01L23/49838 , H01L24/08 , H01L24/16 , H01L25/0655 , H01L2224/08137 , H01L2224/08146 , H01L2224/16157 , H01L2224/16227 , H01L2924/1433 , H01L2924/1436 , H10B80/00
摘要： A semiconductor package is provided, which includes a processor die powered by either a front-side or a backside power delivery network, a plurality of memory dies and control dies stacked over the processor die, a plurality of high-thermal-conductivity interconnects located between and/or placed side-by-side with the dies, a substrate carrying all the dies with the substrate having a first cavity allowing a liquid to pass through, and a cold plate disposed over and in direct thermal contact with the top dies with the cold plate having a second cavity configured to connect to the first cavity and allowing the liquid to flow between the first and second cavities. This semiconductor package can be configured to go beyond the traditional single-sided interconnection and cooling topologies to enable dual- or multi-sided cooling, power supply, and signaling.
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6.发明公开公开(公告)号：US20240027494A1
公开(公告)日：2024-01-25
申请号：US18355255
申请日：2023-07-19
发明人： HO-MING TONG , CHAO-CHUN LU
CPC分类号： G01R1/07342 , G01R1/06783 , G01R3/00
摘要： A probe card system is provided. The probe card system, including a tester assembly, a probe head body configured to couple with the tester assembly, a first interconnection structure on a first side of the probe head body, and a probe layer structure on the first interconnection structure on the first side of the probe head body which is configured to engage with a wafer under test (WUT). The probe layer structure includes a sacrificial layer in connection with the first interconnection structure, a bonding layer in connection with the sacrificial layer, and a plurality of probe tips each in connection with respective conductive patterns exposed from the bonding layer and electrically coupled to the first interconnection structure. The sacrificial layer allows removal of the bonding layer and the plurality of probe tips via an etching operation. A method of manufacturing a probe card system is also provided.
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