公开(公告)号：US4266091A

公开(公告)日：1981-05-05

申请号：US950266

申请日：1978-10-10

Applicant: Sunichi Fukuda

Inventor： Sunichi Fukuda

IPC: H01B7/00 ,  H02G5/00 ,  H05K1/18 ,  H05K3/40

CPC classification number: H05K1/186 ,  H02G5/005 ,  H05K1/145 ,  H05K2201/10015 ,  H05K2201/10272 ,  H05K2201/10643 ,  H05K3/4611

Abstract: A laminated bus bar comprises a pair of elongated flat conductors separated by a layer of insulating material which is provided with longitudinally spaced cut-outs. Capacitors which are comprised of a flat wafer of solid dielectric material are positioned in each of the cut-outs in the layer of insulating material and the capacitor plates are electrically and mechanically connected to the conductors.

Abstract translation: 叠层母线包括一对细长扁平导体，隔开的绝缘材料层具有纵向隔开的切口。 由固体电介质材料的平坦晶片组成的电容器定位在绝缘材料层的每个切口中，并且电容器板电连接和机械连接到导体。

公开(公告)号：US3325379A

公开(公告)日：1967-06-13

申请号：US19677862

申请日：1962-05-22

Applicant: HAZELTINE RESEARCH INC

Inventor： BUSSOLINI JACOB J ,  GUIDA THOMAS P ,  GERALD STONE

IPC: H05K1/09 ,  H05K1/18 ,  H05K3/24 ,  H05K3/32 ,  H05K3/40

CPC classification number: H05K3/4092 ,  H05K1/095 ,  H05K1/184 ,  H05K3/242 ,  H05K3/246 ,  H05K3/32 ,  H05K3/4046 ,  H05K2201/0347 ,  H05K2201/10643 ,  H05K2203/1461

公开(公告)号：US3040214A

公开(公告)日：1962-06-19

申请号：US80416859

申请日：1959-04-06

Applicant: BENDIX CORP

Inventor： MICHAEL SLAVIN ,  HOOTEN JR BASIL P

IPC: H01G2/06 ,  H05K1/11 ,  H05K1/18 ,  H05K3/32

CPC classification number: H01G2/06 ,  H05K1/119 ,  H05K1/184 ,  H05K3/326 ,  H05K2201/09081 ,  H05K2201/09172 ,  H05K2201/09181 ,  H05K2201/09854 ,  H05K2201/1059 ,  H05K2201/10643

公开(公告)号：US2875402A

公开(公告)日：1959-02-24

申请号：US62138956

申请日：1956-11-09

Applicant: HEYER IND INC

Inventor： ST JOHN JOHN H

IPC: F02P17/02 ,  H01G2/00 ,  H05K1/14 ,  H05K1/18 ,  H05K3/34 ,  H05K3/36

CPC classification number: H01G2/00 ,  F02P17/02 ,  H05K1/141 ,  H05K1/184 ,  H05K3/3405 ,  H05K3/366 ,  H05K2201/09172 ,  H05K2201/10446 ,  H05K2201/1053 ,  H05K2201/10643

公开(公告)号：US2869041A

公开(公告)日：1959-01-13

申请号：US62108356

申请日：1956-11-08

Applicant: ADMIRAL CORP

Inventor： DE COLA RINALDO E

IPC: H05K1/11 ,  H05K1/18 ,  H05K3/32 ,  H05K3/34

CPC classification number: H05K3/326 ,  H05K1/119 ,  H05K1/184 ,  H05K3/3447 ,  H05K2201/09081 ,  H05K2201/10295 ,  H05K2201/1059 ,  H05K2201/10643

公开(公告)号：US20160007481A1

公开(公告)日：2016-01-07

申请号：US14798538

申请日：2015-07-14

Applicant: Texas Instruments Incorporated

Inventor： Chikara Azuma

IPC: H05K3/30 ,  H05K3/46 ,  H05K3/42

CPC classification number: H05K3/303 ,  H01G2/065 ,  H01G4/06 ,  H01G4/30 ,  H01L23/49822 ,  H01L23/50 ,  H01L24/16 ,  H01L24/48 ,  H01L24/73 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2224/32014 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48145 ,  H01L2224/48227 ,  H01L2224/73257 ,  H01L2224/73265 ,  H01L2924/00014 ,  H01L2924/01019 ,  H01L2924/01029 ,  H01L2924/10253 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/15787 ,  H01L2924/181 ,  H01L2924/19041 ,  H01L2924/19042 ,  H01L2924/19043 ,  H01L2924/19106 ,  H01L2924/30105 ,  H05K1/0231 ,  H05K1/162 ,  H05K1/181 ,  H05K1/185 ,  H05K3/429 ,  H05K3/4602 ,  H05K3/4644 ,  H05K3/4688 ,  H05K2201/0187 ,  H05K2201/10643 ,  H05K2201/10674 ,  Y10T29/4913 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

Abstract: A method of assembling a packaged semiconductor device starts by dropping a pre-formed capacitor precursor on a surface of or within a first substrate. An integrated circuit die is dropped on either of the first substrate. If the pre-formed capacitor precursor lacks at least a first pair of vias for providing an electrical contact between capacitor plates of said chip capacitor, then at least a first pair of vias is formed in said pre-formed capacitor precursor. The first pair of vias are filled with an electrically conductive material to form the chip capacitor, wherein said filling of said vias provides an electrical contact between said first and second capacitor plates of said chip capacitor and said electrically conductive contact regions on said first substrate. A plurality of electrically conductive material layers and a plurality of dielectric layers are alternately stacked on a second substrate. The plurality of electrically conductive material layers comprise first and second patterns. The first pattern comprises at least a first pair of overlaying areas free of said electrically conductive material, and said second pattern comprises at least a second pair of overlaying areas free of said electrically conductive material. The first pair of areas overlay areas of the second pattern having said electrically conductive material and the second pair of areas overlay areas of the first pattern having said electrically conductive material. The plurality of electrically conductive material layers are electrically isolated from one another by the dielectric layers.

Abstract translation: 组装封装的半导体器件的方法是通过在第一衬底的表面上或在第一衬底的表面上放置预先形成的电容器前体开始的。 集成电路管芯掉在第一衬底中的任一个上。 如果预先形成的电容器前体缺少至少第一对通孔，用于提供所述片状电容器的电容器板之间的电接触，则在所述预形成电容器前体中形成至少第一对通孔。 第一对通孔填充有导电材料以形成片状电容器，其中所述通孔的所述填充提供所述片状电容器的所述第一和第二电容器板与所述第一衬底上的所述导电接触区域之间的电接触。 多个导电材料层和多个电介质层交替堆叠在第二基板上。 多个导电材料层包括第一和第二图案。 第一图案包括至少第一对没有所述导电材料的重叠区域，并且所述第二图案包括至少一个没有导电材料的第二对覆盖区域。 第一对区域覆盖具有所述导电材料的第二图案的区域，并且第二对区域覆盖具有所述导电材料的第一图案的区域。 多个导电材料层通过电介质层彼此电隔离。

公开(公告)号：US09119321B2

公开(公告)日：2015-08-25

申请号：US13305196

申请日：2011-11-28

Applicant: Azuma Chikara

Inventor： Azuma Chikara

IPC: H01G7/00 ,  H05K1/18 ,  H01G2/06 ,  H01G4/06 ,  H01G4/30 ,  H01L23/498 ,  H01L23/50 ,  H05K1/02 ,  H05K1/16 ,  H01L23/00 ,  H05K3/42 ,  H05K3/46

CPC classification number: H05K3/303 ,  H01G2/065 ,  H01G4/06 ,  H01G4/30 ,  H01L23/49822 ,  H01L23/50 ,  H01L24/16 ,  H01L24/48 ,  H01L24/73 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2224/32014 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48145 ,  H01L2224/48227 ,  H01L2224/73257 ,  H01L2224/73265 ,  H01L2924/00014 ,  H01L2924/01019 ,  H01L2924/01029 ,  H01L2924/10253 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/15787 ,  H01L2924/181 ,  H01L2924/19041 ,  H01L2924/19042 ,  H01L2924/19043 ,  H01L2924/19106 ,  H01L2924/30105 ,  H05K1/0231 ,  H05K1/162 ,  H05K1/181 ,  H05K1/185 ,  H05K3/429 ,  H05K3/4602 ,  H05K3/4644 ,  H05K3/4688 ,  H05K2201/0187 ,  H05K2201/10643 ,  H05K2201/10674 ,  Y10T29/4913 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

Abstract: A method of assembling a packaged semiconductor device includes dropping a pre-formed capacitor precursor and an integrated circuit on a surface of a substrate. A pair of vias are formed in the pre-formed capacitor precursor if they don't already exist. The vias are filled with an electrically conductive material to form a chip capacitor. The filling of the vias provides an electrical contact between capacitor plates of the chip capacitor and electrically conductive contact regions on the substrate.

Abstract translation: 一种组装封装半导体器件的方法包括将预先形成的电容器前体和集成电路放在衬底的表面上。 如果它们不存在，则在预先形成的电容器前体中形成一对通孔。 通孔填充有导电材料以形成片状电容器。 通孔的填充提供了片状电容器的电容器板和衬底上的导电接触区域之间的电接触。

公开(公告)号：US08686826B2

公开(公告)日：2014-04-01

申请号：US13080570

申请日：2011-04-05

Applicant: Daniel A. Chandler ,  Matthew P. Galla

Inventor： Daniel A. Chandler ,  Matthew P. Galla

IPC: H01C7/10 ,  H01C1/14

CPC classification number: H01C1/1406 ,  H01C1/144 ,  H01C7/02 ,  H05K3/328 ,  H05K2201/10492 ,  H05K2201/10643

Abstract: A surface mount circuit protection device includes a laminar PTC resistive element having first and second major surfaces and a thickness therebetween. A first electrode layer substantially coextensive the first surface is formed of a first metal material of a type adapted to be soldered to a printed circuit substrate. A second electrode layer formed at the second major surface includes structure forming or defining a weld plate. The metal weld plate has a thermal mass and thickness capable of withstanding resistance micro spot welding of a strap interconnect without significant resultant damage to the device. The device is preferably surface mounted to a printed circuit board assembly forming a battery protection circuit connected to a battery/cell by battery strap interconnects, wherein one of the battery strap interconnects is micro spot welded to the weld plate of the device.

Abstract translation: 表面安装电路保护装置包括具有第一和第二主表面的层状PTC电阻元件和它们之间的厚度。 基本上共同延伸第一表面的第一电极层由适于焊接到印刷电路基板的第一金属材料形成。 形成在第二主表面处的第二电极层包括形成或限定焊接板的结构。 金属焊接板具有热质量和厚度，能够耐受带状互连的电阻微点焊，而不会对器件造成严重的损害。 该装置优选地表面安装到印刷电路板组件，其形成通过电池带互连连接到电池/电池的电池保护电路，其中电池带互连中的一个被微点焊接到装置的焊接板。

公开(公告)号：US20140055968A1

公开(公告)日：2014-02-27

申请号：US14069054

申请日：2013-10-31

Applicant: Kong-Chen Chen

Inventor： Kong-Chen Chen

IPC: H05K1/11 ,  H05K3/30 ,  H05K3/34 ,  H05K1/18

CPC classification number: H05K1/111 ,  H01L23/64 ,  H01L2224/04105 ,  H01L2224/20 ,  H01L2924/19103 ,  H01L2924/19104 ,  H05K1/0231 ,  H05K1/0233 ,  H05K1/0234 ,  H05K1/181 ,  H05K3/301 ,  H05K3/341 ,  H05K2201/086 ,  H05K2201/10515 ,  H05K2201/1053 ,  H05K2201/10636 ,  H05K2201/10643 ,  H05K2201/10674 ,  H05K2201/10719 ,  Y02P70/611 ,  Y10T29/4902 ,  Y10T29/4913 ,  Y10T29/49144

Abstract: An electronic device is presented for electrical connection between a first pad contact of an integrated circuit component and a target contact positioned substantially in a first plane of a target platform. The electronic device includes a first surface substantially parallel to the first plane and a second surface below the first surface substantially parallel to the first plane. The first surface includes a first contact region configured to connect to the first pad contact when the electronic device is connected between the first pad contact and the target contact. The second surface includes a second contact region configured to connect to the target contact when the electronic device is connected between the first pad contact and the target contact. The electronic device further includes a multitude of electrically passive elements connected between the first and second contact regions.

Abstract translation: 呈现电子设备用于集成电路部件的第一焊盘触点和基本上位于目标平台的第一平面中的目标触点之间的电连接。 电子设备包括基本上平行于第一平面的第一表面和基本上平行于第一平面的第一表面下方的第二表面。 第一表面包括第一接触区域，被配置为当电子设备连接在第一焊盘触点和目标触点之间时连接到第一焊盘触点。 第二表面包括被配置为当电子设备连接在第一焊盘触点和目标触点之间时连接到目标触点的第二触点区域。 电子设备还包括连接在第一和第二接触区域之间的多个电动无源元件。

公开(公告)号：US08593825B2

公开(公告)日：2013-11-26

申请号：US12631649

申请日：2009-12-04

Applicant: Kong-Chen Chen

Inventor： Kong-Chen Chen

IPC: H05K7/10

CPC classification number: H05K1/111 ,  H01L23/64 ,  H01L2224/04105 ,  H01L2224/20 ,  H01L2924/19103 ,  H01L2924/19104 ,  H05K1/0231 ,  H05K1/0233 ,  H05K1/0234 ,  H05K1/181 ,  H05K3/301 ,  H05K3/341 ,  H05K2201/086 ,  H05K2201/10515 ,  H05K2201/1053 ,  H05K2201/10636 ,  H05K2201/10643 ,  H05K2201/10674 ,  H05K2201/10719 ,  Y02P70/611 ,  Y10T29/4902 ,  Y10T29/4913 ,  Y10T29/49144

Abstract: A manufacturing technique for constructing passive electronic components in vertical configurations is disclosed. Electrically passive components are constructed in a structure that is substantially perpendicular to target platform including a first plane to provide a larger electrode contact area and a smaller physical dimension. Passive components structured to be substantially perpendicular to a plane associated with a target platform can be directly connected to pad contacts of an integrated circuit or substrate or can be embedded in a package to reduce the area overhead of a passive component while improving the effectiveness of the passive components in their applications.

Abstract translation: 公开了用于构造垂直配置的无源电子部件的制造技术。 电动无源部件构造成基本上垂直于包括第一平面的靶平台的结构，以提供更大的电极接触面积和更小的物理尺寸。 被构造为基本上垂直于与目标平台相关的平面的被动部件可以直接连接到集成电路或基板的焊盘触点，或者可以嵌入封装中以减少被动部件的面积开销，同时提高 被动元件在其应用中。