公开(公告)号：US09893688B1

公开(公告)日：2018-02-13

申请号：US15299527

申请日：2016-10-21

Applicant: STMicroelectronics, Inc.

Inventor： Pavan Nallamothu

IPC: H03F1/02 ,  H03F3/45 ,  H03F1/34

CPC classification number: H03F3/45219 ,  H03F1/342 ,  H03F2200/411 ,  H03F2203/45048 ,  H03F2203/45212

Abstract: A differential amplifier has an inherent offset voltage. In many circuit applications, such as with a voltage to current converter circuit, it is important to nullify that offset voltage. A calibration circuit is provided to configured the differential amplifier to operate as a comparator with a common voltage applied to both inputs. The logic state of the output of the amplifier indicates whether the offset voltage is positive or negative. In response thereto, a trim current with a progressively increasing magnitude is injected into the amplifier and the amplifier output is monitored to detect a change in logic state. The magnitude of the trim current at the point where the logic state changes is the magnitude of trim current needed to nullify the voltage offset.

公开(公告)号：US09893147B2

公开(公告)日：2018-02-13

申请号：US15345250

申请日：2016-11-07

Applicant: STMICROELECTRONICS, INC.

Inventor： Nicolas Loubet ,  Prasanna Khare

IPC: H01L27/01 ,  H01L29/06 ,  H01L21/762 ,  H01L21/8234 ,  H01L27/088 ,  H01L29/16 ,  H01L29/49 ,  H01L21/02 ,  H01L21/3065 ,  H01L21/308 ,  H01L21/3105 ,  H01L29/08 ,  H01L29/165 ,  H01L29/66 ,  H01L29/78

CPC classification number: H01L29/0653 ,  H01L21/02532 ,  H01L21/02661 ,  H01L21/3065 ,  H01L21/308 ,  H01L21/31053 ,  H01L21/762 ,  H01L21/76224 ,  H01L21/823418 ,  H01L21/823431 ,  H01L21/823481 ,  H01L27/0886 ,  H01L29/0847 ,  H01L29/16 ,  H01L29/165 ,  H01L29/49 ,  H01L29/66545 ,  H01L29/7848

Abstract: Channel-to-substrate leakage in a FinFET device is prevented by inserting an insulating layer between the semiconducting channel and the substrate during fabrication of the device. Similarly, source/drain-to-substrate leakage in a FinFET device is prevented by isolating the source/drain regions from the substrate by inserting an insulating layer between the source/drain regions and the substrate. Forming such an insulating layer isolates the conduction path from the substrate both physically and electrically, thus preventing current leakage. In an array of semiconducting fins made up of a multi-layer stack, the bottom material is removed thus yielding a fin array that is suspended above the silicon surface. A resulting gap underneath the remaining top fin material is then filled with oxide to better support the fins and to isolate the array of fins from the substrate.

公开(公告)号：US09876110B2

公开(公告)日：2018-01-23

申请号：US14169875

申请日：2014-01-31

Applicant: STMicroelectronics, Inc.

Inventor： Jocelyne Gimbert

IPC: H01L27/12 ,  H01L21/8238 ,  H01L29/78 ,  H01L21/70 ,  H01L21/84 ,  H01L21/265 ,  H01L29/66 ,  H01L21/324 ,  H01L29/16 ,  H01L29/161 ,  H01L29/165

CPC classification number: H01L29/7848 ,  H01L21/26506 ,  H01L21/26513 ,  H01L21/324 ,  H01L21/707 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/84 ,  H01L27/1203 ,  H01L29/1608 ,  H01L29/161 ,  H01L29/165 ,  H01L29/66628 ,  H01L29/66772 ,  H01L29/66795

Abstract: Methods and structures for forming highly-doped, ultrathin layers for transistors formed in semiconductor-on-insulator substrates are described. High dopant concentrations may be achieved in ultrathin semiconductor layers to improve device characteristics. Ion implantation at elevated temperatures may mitigate defect formation for stoichiometric dopant concentrations up to about 30%. In-plane stressors may be formed adjacent to channels of transistors formed in ultrathin semiconductor layers.

公开(公告)号：US09860160B2

公开(公告)日：2018-01-02

申请号：US14984620

申请日：2015-12-30

Applicant: STMICROELECTRONICS, INC.

Inventor： Jonathan Evans ,  Lee Johnson ,  Amit Kumar Aggarwal

IPC: H04L12/66 ,  H04L12/707 ,  H04L12/801 ,  H04L12/46

CPC classification number: H04L45/24 ,  H04L12/4641 ,  H04L47/17

Abstract: A method and apparatus for multipath switching using per-hop virtual local area network (VLAN) remapping is disclosed. In the method and apparatus, a data packet is forwarded for transmission over one of a first port and a second port. The device identifies a VLAN ID of the data packet as a second VLAN ID and changes the second VLAN ID to a first VLAN ID. Then one or more criteria of a classification set entry for forwarding the data packet over the second port are evaluated. The data packet is forwarded over the second port if the criteria are met and the data packet is associated with the second VLAN ID. Alternatively, the data packet is forwarded over the first port and is associated with the first VLAN ID if a dynamic entry specifies the data packet is to be forwarded over the first port.

公开(公告)号：US09859423B2

公开(公告)日：2018-01-02

申请号：US14587655

申请日：2014-12-31

Applicant: STMICROELECTRONICS, INC. ,  GLOBALFOUNDRIES INC. ,  INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Qing Liu ,  Ruilong Xie ,  Chun-chen Yeh ,  Xiuyu Cai

IPC: H01L29/165 ,  H01L29/78 ,  H01L29/66 ,  H01L29/417

CPC classification number: H01L29/7848 ,  H01L29/165 ,  H01L29/41783 ,  H01L29/6681 ,  H01L29/7842 ,  H01L29/7851

Abstract: A hetero-channel FinFET device provides enhanced switching performance over a FinFET device having a silicon channel, and is easier to integrate into a fabrication process than is a FinFET device having a germanium channel. A FinFET device featuring the heterogeneous Si/SiGe channel includes a fin having a central region made of silicon and sidewall regions made of SiGe. A hetero-channel pFET device in particular has higher carrier mobility and less gate-induced drain leakage current than either a silicon device or a SiGe device. The hetero-channel FinFET permits the SiGe portion of the channel to have a Ge concentration in the range of about 25-40% and permits the fin height to exceed 40 nm while remaining stable.

公开(公告)号：US09842794B2

公开(公告)日：2017-12-12

申请号：US14945291

申请日：2015-11-18

Applicant: STMICROELECTRONICS, INC.

Inventor： Ela Mia Cadag ,  Jefferson Talledo

IPC: H01L23/495 ,  H01L23/31 ,  H01L21/56 ,  H01L23/00

CPC classification number: H01L23/4952 ,  H01L21/4828 ,  H01L21/56 ,  H01L21/561 ,  H01L23/3107 ,  H01L23/3121 ,  H01L23/4951 ,  H01L23/49548 ,  H01L23/49568 ,  H01L23/49582 ,  H01L24/16 ,  H01L24/32 ,  H01L24/48 ,  H01L24/81 ,  H01L24/83 ,  H01L24/97 ,  H01L2224/16245 ,  H01L2224/2919 ,  H01L2224/32245 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/48465 ,  H01L2224/73204 ,  H01L2224/73265 ,  H01L2224/81002 ,  H01L2224/81986 ,  H01L2224/83002 ,  H01L2224/83101 ,  H01L2224/83385 ,  H01L2224/83986 ,  H01L2224/92125 ,  H01L2224/97 ,  H01L2924/00014 ,  H01L2924/157 ,  H01L2924/181 ,  H01L2224/45099 ,  H01L2924/00012 ,  H01L2924/0665 ,  H01L2224/13099 ,  H01L2924/00

Abstract: One or more embodiments are directed to semiconductor packages having an integrated heatsink and methods of forming same. In one embodiment, a package includes a plurality of leads that support and enclose periphery portions of the semiconductor die. The leads have first and second, opposing surfaces that form outer surfaces of the package. The first surface of the leads may form a heatsink and the second surface of the leads form lands of the package for coupling to another device, substrate, or board. The package includes encapsulation material that surrounds the semiconductor die and located between upper portions of the leads. The package further includes a back filling material (or insulating material) that is below the semiconductor die and between lower portions of the leads.

公开(公告)号：US09841341B2

公开(公告)日：2017-12-12

申请号：US14861648

申请日：2015-09-22

Applicant: STMICROELECTRONICS S.R.L. ,  STMICROELECTRONICS, INC.

Inventor： Fulvio Vittorio Fontana ,  Jefferson Talledo

IPC: H01L21/50 ,  H01L23/498 ,  G01L19/14 ,  B81B7/00 ,  B81C1/00 ,  H01L23/057 ,  H01L23/495

CPC classification number: G01L19/148 ,  B81B7/0045 ,  B81C1/00325 ,  H01L21/50 ,  H01L23/057 ,  H01L23/49575 ,  H01L23/49861 ,  H01L2224/48091 ,  H01L2224/73265 ,  H01L2224/8592 ,  H01L2924/00014

Abstract: A surface mounting device has one body of semiconductor material such as an ASIC, and a package surrounding the body. The package has a base region carrying the body, a cap and contact terminals. The base region has a Young's modulus lower than 5 MPa. For forming the device, the body is attached to a supporting frame including contact terminals and a die pad, separated by cavities; bonding wires are soldered to the body and to the contact terminals; an elastic material is molded so as to surround at least in part lateral sides of the body, fill the cavities of the supporting frame and cover the ends of the bonding wires on the contact terminals; and a cap is fixed to the base region. The die pad is then etched away.

公开(公告)号：US09837320B2

公开(公告)日：2017-12-05

申请号：US15582962

申请日：2017-05-01

Applicant: STMicroelectronics, Inc.

Inventor： John C. Pritiskutch ,  Richard Hildenbrandt

IPC: H01L21/82 ,  H01L21/8234 ,  H01L21/265 ,  H01L21/324 ,  H01L21/225 ,  H01L21/266 ,  H01L27/088 ,  H01L29/10 ,  H01L29/78

CPC classification number: H01L21/823493 ,  H01L21/2253 ,  H01L21/26513 ,  H01L21/266 ,  H01L21/324 ,  H01L21/823412 ,  H01L21/823487 ,  H01L27/088 ,  H01L29/1083 ,  H01L29/7827

Abstract: First and second transistors with different electrical characteristics are supported by a substrate having a first-type dopant. The first transistor includes a well region within the substrate having the first-type dopant, a first body region within the well region having a second-type dopant and a first source region within the first body region and laterally offset from the well region by a first channel. The second transistor includes a second body region within the semiconductor substrate layer having the second-type dopant and a second source region within the second body region and laterally offset from material of the substrate by a second channel having a length greater than the length of the first channel. A gate region extends over portions of the first and second body regions for the first and second channels, respectively.

公开(公告)号：US09826434B2

公开(公告)日：2017-11-21

申请号：US13710321

申请日：2012-12-10

Applicant: STMicroelectronics, Inc.

Inventor： Liwen Chu ,  George A. Vlantis

IPC: H04W28/20 ,  H04W28/22

CPC classification number: H04W28/20

Abstract: Methods and systems are disclosed for the operation of wireless communication networks, in which communication channels can have possibly overlapping bandwidths of different sizes, including sensor networks operating by the IEEE 802.11ah standard. A first method of signaling to negotiate the channel bandwidth conveys the needed information in the SIG field of the PPDUs of duplicate RTS/CTS frames, and uses the SIG field of PPDUs of duplicated data, control and management frames to perform transmit opportunity protection. A second method of signaling to negotiate the channel bandwidth conveys the needed information in the scrambling sequence field of PPDUs of duplicate RTS, and uses the scrambling sequence field of PPDUs of duplicated data, control and management frames to perform transmit opportunity protection.

公开(公告)号：US09818930B2

公开(公告)日：2017-11-14

申请号：US14938432

申请日：2015-11-11

Applicant: STMicroelectronics, Inc.

Inventor： John Hongguang Zhang

IPC: H01L41/332 ,  B23P15/00 ,  C03C25/00 ,  C23F1/00 ,  H01L41/09

CPC classification number: H01L41/332 ,  H01L41/0973

Abstract: A support structure includes an internal cavity. An elastic membrane extends to divide the internal cavity into a first chamber and a second chamber. The elastic membrane includes a nanometric-sized pin hole extending there through to interconnect the first chamber to the second chamber. The elastic membrane is formed of a first electrode film and a second electrode film separated by a piezo insulating film. Electrical connection leads are provided to support application of a bias current to the first and second electrode films of the elastic membrane. In response to an applied bias current, the elastic membrane deforms by bending in a direction towards one of the first and second chambers so as to produce an increase in a diameter of the pin hole.