公开(公告)号：US20030015760A1

公开(公告)日：2003-01-23

申请号：US09908695

申请日：2001-07-20

Applicant: Motorola, Inc.

Inventor： Jay A. Curless ,  Albert A. Talin

IPC: H01L021/8238 ,  H01L029/76 ,  H01L029/94 ,  H01L031/062 ,  H01L031/113 ,  H01L031/119

CPC classification number: H01L21/8258 ,  H01L21/02197 ,  H01L21/02381 ,  H01L21/02488 ,  H01L21/02505 ,  H01L21/02513 ,  H01L21/02521 ,  H01L21/31691 ,  H01L21/324

Abstract: Process for fabricating a semiconductor structure (500) comprising depositing a capping layer (67) on a portion (54) of a monocrystalline compound semiconductor layer (66) overlying a template film (64), a monocrystalline perovskite oxide material (60), an amorphous oxide layer (62) and a monocrystalline silicon substrate (52), and then exposing at least one surface region (531) of the single crystal silicon substrate (52) into which a CMOS circuit (56) is formed in a CMOS region (53), followed by heating the CMOS circuit (56) to anneal the CMOS region (53) and, optionally, concurrently transform the monocrystalline perovskite oxide film (60) into an amorphous perovskite oxide film (136). The resulting composite semiconductor structure (500) is also encompassed.

Abstract translation: 一种用于制造半导体结构（500）的方法，包括在覆盖在模板膜（64）上的单晶化合物半导体层（66）的一部分（54）上沉积覆盖层（67），单晶钙钛矿氧化物材料（60）， 非晶氧化物层（62）和单晶硅衬底（52），然后暴露在CMOS区域中形成有CMOS电路（56）的单晶硅衬底（52）的至少一个表面区域（531） 53），然后加热CMOS电路（56）以退火CMOS区域（53），并且任选地同时将单晶钙钛矿氧化物膜（60）转变成无定形钙钛矿氧化物膜（136）。 所得的复合半导体结构（500）也包括在内。

公开(公告)号：US20030015731A1

公开(公告)日：2003-01-23

申请号：US09910020

申请日：2001-07-23

Applicant: Motorola, Inc.

Inventor： Jay A. Curless ,  Lyndee L. Hilt ,  Albert A. Talin

IPC: H01L031/109

CPC classification number: H01L21/31691 ,  H01L21/02197 ,  H01L21/02381 ,  H01L21/02488 ,  H01L21/02505 ,  H01L21/02513 ,  H01L21/02521

Abstract: Process for fabricating a semiconductor structure (34), and the resulting products, having reduced crystal defects and/or contamination in a monocrystalline compound semiconductor layer (26) that is compliantly attached to a monocrystalline semiconductor substrate (22) via an accommodating buffer layer (36), a capping/template layer (30), and a thin monocrystalline compound semiconductor seed film (38) comprised of a compound semiconductor, in that order from furthest to closest to layer (26). To accomplish this, a thin monocrystalline compound semiconductor seed film (38) is formed on an intermediate structure (33) including a monocrystalline perovskite buffer layer (24) and an overlying capping/template layer (30), and the resulting structure (33) is annealed at a temperature effective to reduce crystal defects in the compound semiconductor seed film (38), and optionally also may be used to amorphize the monocrystalline perovskite layer, all before a compound semiconductor layer (26) is formed thereon in a device-thickness.

Abstract translation: 制造半导体结构（34）的方法以及所得产品具有通过容纳缓冲层顺应地附接到单晶半导体衬底（22）的单晶化合物半导体层（26）中具有减小的晶体缺陷和/或污染 36），封盖/模板层（30）和由化合物半导体构成的薄单晶化合物半导体种子膜（38），其从最远到最靠近层（26）的顺序。 为了实现这一点，在包括单晶钙钛矿缓冲层（24）和上覆盖/模板层（30）的中间结构（33）上形成薄单晶化合物半导体种子膜（38），所得结构（33） 在有效地减少化合物半导体种子膜（38）中的晶体缺陷的温度下进行退火，并且任选地还可以将其用于非晶化单晶钙钛矿层，所有这些都是在其上形成化合物半导体层（26）之前的器件厚度 。

公开(公告)号：US20030015725A1

公开(公告)日：2003-01-23

申请号：US09908886

申请日：2001-07-20

Applicant: MOTOROLA, INC.

Inventor： Ravindranath Droopad ,  Joyce Yamamoto ,  Zhiyi Yu

IPC: H01L029/74

CPC classification number: H01L21/02488 ,  C30B25/02 ,  C30B25/18 ,  C30B29/40 ,  C30B29/403 ,  C30B29/406 ,  H01L21/02381 ,  H01L21/02505 ,  H01L21/02513 ,  H01L21/02521 ,  H01L21/02694 ,  H01L21/31691

Abstract: High quality epitaxial layers of monocrystalline materials can be grown overlying monocrystalline substrates such as large silicon wafers by forming a compliant substrate for growing the monocrystalline layers. An accommodating buffer layer comprises a layer of monocrystalline oxide spaced apart from a silicon wafer by an amorphous interface layer of silicon oxide. The amorphous interface layer dissipates strain and permits the growth of a high quality monocrystalline oxide accommodating buffer layer. The accommodating buffer layer is lattice matched to both the underlying silicon wafer and the overlying monocrystalline material layer. Any lattice mismatch between the accommodating buffer layer and the underlying silicon substrate is taken care of by the amorphous interface layer. In addition, formation of a compliant substrate may include utilizing ion beam assisted deposition, surfactant enhanced epitaxy, epitaxial growth of single crystal silicon onto single crystal oxide, and epitaxial growth of Zintl phase materials.

Abstract translation: 通过形成用于生长单晶层的柔性衬底，可以将单晶材料的高质量外延层生长在覆盖单晶衬底（例如大硅晶片）上。 容纳缓冲层包括通过硅氧化物的非晶界面层与硅晶片间隔开的单晶氧化物层。 非晶界面层消耗应变并允许高质量单晶氧化物容纳缓冲层的生长。 容纳缓冲层与下面的硅晶片和上覆的单晶材料层晶格匹配。 通过非晶界面层处理容纳缓冲层和底层硅衬底之间的任何晶格失配。 此外，顺应性衬底的形成可以包括利用离子束辅助沉积，表面活性剂增强外延，将单晶硅外延生长到单晶氧化物上，以及Zintl相材料的外延生长。

公开(公告)号：US20030015711A1

公开(公告)日：2003-01-23

申请号：US09908892

申请日：2001-07-20

Applicant: Motorola, Inc.

Inventor： Albert A. Talin ,  Lyndee L. Hilt ,  Alexander A. Demkov

IPC: H01L029/04

CPC classification number: H01L27/0605 ,  H01L21/02381 ,  H01L21/02488 ,  H01L21/02505 ,  H01L21/02513 ,  H01L21/02521 ,  H01L21/8258

Abstract: High quality epitaxial layers of monocrystalline materials can be grown overlying monocrystalline substrates such as large silicon wafers by forming a compliant substrate for growing the monocrystalline layers. An accommodating buffer layer comprises a layer of monocrystalline oxide spaced apart from a silicon wafer by an amorphous interface layer of silicon oxide. The amorphous interface layer dissipates strain and permits the growth of a high quality monocrystalline oxide accommodating buffer layer. The accommodating buffer layer is lattice matched to both the underlying silicon wafer and the overlying monocrystalline material layer. Any lattice mismatch between the accommodating buffer layer and the underlying silicon substrate is taken care of by the amorphous interface layer. In addition, formation of a compliant substrate includes utilizing an intermetallic layer of an intermetallic compound material.

Abstract translation: 通过形成用于生长单晶层的柔性衬底，可以将单晶材料的高质量外延层生长在覆盖单晶衬底（例如大硅晶片）上。 容纳缓冲层包括通过硅氧化物的非晶界面层与硅晶片间隔开的单晶氧化物层。 非晶界面层消耗应变并允许高质量单晶氧化物容纳缓冲层的生长。 容纳缓冲层与下面的硅晶片和上覆的单晶材料层晶格匹配。 通过非晶界面层处理容纳缓冲层和底层硅衬底之间的任何晶格失配。 此外，顺应性衬底的形成包括利用金属间化合物材料的金属间化合物层。

公开(公告)号：US20030015710A1

公开(公告)日：2003-01-23

申请号：US09908888

申请日：2001-07-20

Applicant: MOTOROLA, INC.

Inventor： Amarildo J.C. Vieira ,  Barbara F. Barenburg ,  Timothy J. Brophy

IPC: H01L031/0256

CPC classification number: H01S5/0687 ,  H01L21/02381 ,  H01L21/02488 ,  H01L21/02505 ,  H01L21/02513 ,  H01L21/02521 ,  H01L21/8258 ,  H01L27/0605 ,  H01S5/021 ,  H01S5/0261 ,  H01S5/0264

Abstract: High quality epitaxial layers of monocrystalline materials can be grown overlying monocrystalline substrates such as large silicon wafers by forming a compliant substrate for growing the monocrystalline layers. An accommodating buffer layer comprises a layer of monocrystalline oxide spaced apart from a silicon wafer by an amorphous interface layer of silicon oxide. The amorphous interface layer dissipates strain and permits the growth of a high quality monocrystalline oxide accommodating buffer layer. The accommodating buffer layer is lattice matched to both the underlying silicon wafer and the overlying monocrystalline material layer. Any lattice mismatch between the accommodating buffer layer and the underlying silicon substrate is taken care of by the amorphous interface layer. In addition, formation of a compliant substrate may include utilizing surfactant enhanced epitaxy, epitaxial growth of single crystal silicon onto single crystal oxide, and epitaxial growth of Zintl phase materials. A wavelength locker for stabilizing a wavelength of an optical output signal from an optical transmitter is formed overlying the silicon wafer.

Abstract translation: 通过形成用于生长单晶层的柔性衬底，可以将单晶材料的高质量外延层生长在覆盖单晶衬底（例如大硅晶片）上。 容纳缓冲层包括通过硅氧化物的非晶界面层与硅晶片间隔开的单晶氧化物层。 非晶界面层消耗应变并允许高质量单晶氧化物容纳缓冲层的生长。 容纳缓冲层与下面的硅晶片和上覆的单晶材料层晶格匹配。 通过非晶界面层处理容纳缓冲层和底层硅衬底之间的任何晶格失配。 此外，顺应性衬底的形成可以包括利用表面活性剂增强的外延，将单晶硅外延生长到单晶氧化物上，以及Zintl相材料的外延生长。 用于稳定来自光发送器的光输出信号的波长的波长锁定器形成在硅晶片上。

公开(公告)号：US20030015700A1

公开(公告)日：2003-01-23

申请号：US09908860

申请日：2001-07-20

Applicant: MOTOROLA, INC.

Inventor： Kurt W. Eisenbeiser ,  Thomas Freeburg ,  E. James Prendergast ,  William J. Ooms ,  Ravindranath Droopad ,  Jamal Ramdani

IPC: H01L029/04 ,  H01L031/036 ,  H01L031/0376

CPC classification number: H01L31/0693 ,  H01L21/02164 ,  H01L21/02197 ,  H01L21/02378 ,  H01L21/02381 ,  H01L21/02395 ,  H01L21/02488 ,  H01L21/02543 ,  H01L21/02546 ,  H01L21/02551 ,  H01L21/31691 ,  H01L21/8221 ,  H01L23/66 ,  H01L31/0687 ,  H01L2924/0002 ,  Y02E10/544 ,  H01L2924/00

Abstract: Multijunction solar cell structures (100) including high quality epitaxial layers of monocrystalline semiconductor materials that are grown overlying monocrystalline substrates (102) such as large silicon wafers by forming a compliant substrate for growing the monocrystalline layers are disclosed. One way to achieve the formation of a compliant substrate includes first growing an accommodating buffer layer (104) on a silicon wafer. The accommodating buffer (104) layer is a layer of monocrystalline material spaced apart from the silicon wafer by an amorphous interface layer (112) of silicon oxide. The amorphous interface layer (112) dissipates strain and permits the growth of a high quality monocrystalline oxide accommodating buffer layer. Multiple and varied accommodating buffer layers can be used to achieve the monolithic integration of multiple non-lattice matched solar cell junctions.

Abstract translation: 公开了包括通过形成用于生长单晶层的柔性衬底生长在单晶衬底（102）如大硅晶片上的单质半导体材料的高质量外延层的多结太阳能电池结构（100）。 实现顺应性衬底的形成的一种方法包括首先在硅晶片上生长容纳缓冲层（104）。 容纳缓冲器（104）层是通过氧化硅的非晶界面层（112）与硅晶片间隔开的单晶材料层。 非晶界面层（112）耗散应变并允许高质量单晶氧化物容纳缓冲层的生长。 可以使用多个不同的容纳缓冲层来实现多个非晶格匹配的太阳能电池接头的单片集成。

公开(公告)号：US20030013218A1

公开(公告)日：2003-01-16

申请号：US09900883

申请日：2001-07-10

Applicant: Motorola, Inc.

Inventor： Marc Chason

IPC: H01L029/06 ,  H01L031/0328 ,  H01L021/00 ,  H01L031/0336 ,  H01L031/072 ,  H01L031/109 ,  H01L031/062 ,  H01L031/113

CPC classification number: H01L27/0688 ,  C30B25/18 ,  H01L21/02381 ,  H01L21/02488 ,  H01L21/02505 ,  H01L21/02513 ,  H01L21/02521 ,  H01L21/8221 ,  H01L21/8258 ,  H01L27/0605 ,  H01L2924/00011 ,  H01S5/021 ,  H01S5/0262 ,  H01S5/0264 ,  H01S2301/173 ,  H01L2224/80001

Abstract: High quality epitaxial layers of monocrystalline materials can be grown overlying monocrystalline substrates such as large silicon wafers by forming a compliant substrate for growing the monocrystalline layers. An accommodating buffer layer comprises a layer of monocrystalline oxide spaced apart from a silicon wafer by an amorphous interface layer of silicon oxide. The amorphous interface layer dissipates strain and permits the growth of a high quality monocrystalline oxide accommodating buffer layer. The accommodating buffer layer is lattice matched to both the underlying silicon wafer and the overlying monocrystalline material layer. Any lattice mismatch between the accommodating buffer layer and the underlying silicon substrate is taken care of by the amorphous interface layer. In addition, formation of a compliant substrate may include utilizing surfactant enhanced epitaxy, epitaxial growth of single crystal silicon onto single crystal oxide, and epitaxial growth of Zintl phase materials.

Abstract translation: 通过形成用于生长单晶层的柔性衬底，可以将单晶材料的高质量外延层生长在覆盖单晶衬底（例如大硅晶片）上。 容纳缓冲层包括通过硅氧化物的非晶界面层与硅晶片间隔开的单晶氧化物层。 非晶界面层消耗应变并允许高质量单晶氧化物容纳缓冲层的生长。 容纳缓冲层与下面的硅晶片和上覆的单晶材料层晶格匹配。 通过非晶界面层处理容纳缓冲层和底层硅衬底之间的任何晶格失配。 此外，顺应性衬底的形成可以包括利用表面活性剂增强的外延，将单晶硅外延生长到单晶氧化物上，以及Zintl相材料的外延生长。

公开(公告)号：US20030012965A1

公开(公告)日：2003-01-16

申请号：US09901109

申请日：2001-07-10

Applicant: MOTOROLA, INC.

Inventor： Ravindranath Droopad ,  Scott T. Massie

IPC: B32B009/00

CPC classification number: H01L21/02521 ,  C30B25/18 ,  H01L21/02381 ,  H01L21/02439 ,  H01L21/02488 ,  H01L21/02505 ,  H01L21/02513 ,  Y10T428/265

Abstract: High quality epitaxial layers of monocrystalline materials can be grown overlying monocrystalline substrates such as large silicon wafers by forming a compliant substrate for growing the monocrystalline layers. An accommodating buffer layer is lattice matched to the overlying monocrystalline material layer. In addition, formation of a compliant substrate may include utilizing a monocrystalline oxygen-doped material layer. The monocrystalline oxygen-doped material layer may prevent contamination of the accommodating buffer layer and may facilitate isolation of devices formed in the overlying monocrystalline material. Further, the monocrystalline oxygen-doped materials may be highly resistive and could reduce or eliminate backgating and sidegating effects.

Abstract translation: 通过形成用于生长单晶层的柔性衬底，可以将单晶材料的高质量外延层生长在覆盖单晶衬底（例如大硅晶片）上。 容纳缓冲层与上覆单晶材料层晶格匹配。 此外，顺应性衬底的形成可以包括利用单晶氧掺杂材料层。 单晶氧掺杂材料层可以防止容纳缓冲层的污染，并且可以促进在上层单晶材料中形成的器件的隔离。 此外，单晶氧掺杂材料可以是高电阻性的并且可以减少或消除背部和侧面效应。

公开(公告)号：US20030012925A1

公开(公告)日：2003-01-16

申请号：US09905110

申请日：2001-07-16

Applicant: MOTOROLA, INC.

Inventor： Jonathan F. Gorrell

IPC: H01L031/112 ,  B32B003/10 ,  H01L029/76 ,  H01L031/036

CPC classification number: H01L21/76898 ,  H01L21/02381 ,  H01L21/02488 ,  H01L21/02505 ,  H01L21/02513 ,  H01L21/02521 ,  H01L21/30608 ,  H01L21/31111 ,  H01L21/8258 ,  H01L27/0605 ,  H01L2924/0002 ,  Y10T428/24322 ,  Y10T428/24331 ,  H01L2924/00

Abstract: Highly controlled, highly aligned monolithic integration of devices in a high quality monocrystalline material layer (26) with vias (211, 231) fabricated in an underlying monocrystalline substrate (22) in a single monolithic three dimensional architecture (20, 34). Excellent compliancy is achieved in a monolithic semiconductor structure (20, 34) by processes described herein while at the same time fabrication of via openings (211, 231) in the monocrystalline substrate (20, 34) can be made in a controlled, aligned manner to the back side (263) of a high quality monocrystalline film (26). Conductive connections (219, 239) can be made to devices (271, 273) in the high quality monocrystalline layer (26) from its backside (263).

Abstract translation: 高度对齐的高度对齐的单体集成器件在高质量的单晶材料层（26）中，其中通孔（211,231）在单个单片三维架构（20,34）中制造在下面的单晶衬底（22）中。 通过本文所述的工艺，在单片半导体结构（20,34）中实现了优异的兼容性，同时可以以受控对准的方式制造单晶衬底（20,34）中的通孔开口（211,231），同时 到高质量单晶膜（26）的背面（263）。 导电连接（219,239）可以从其背面（263）制成高质量单晶层（26）中的器件（271,273）。

公开(公告)号：US20030012286A1

公开(公告)日：2003-01-16

申请号：US09902124

申请日：2001-07-10

Applicant: MOTOROLA, INC.

Inventor： Faisal Ishtiaq ,  Bhavan Gandhi ,  Kevin O'Connell

IPC: H04N007/12

CPC classification number: H04N19/89 ,  H04N19/895

Abstract: A method and device for detecting errors in a digital video signal comprising a sequence of image frames, each image frame comprising a sequence of image slices, each image slice comprising a sequence of macroblocks and each macroblock comprising a plurality of pixels. A macroblock decoder includes an error detection unit that operates to calculate an error metric between pixel values on at least part of the boundary between a current macroblock and one or more adjoining macroblocks and to label the current macroblock as suspicious if the error metric is greater than a threshold level. The threshold level is adjusted according to a weighted average error metric from one or more previous image frames. Suspicious macroblocks and subsequent inter-coded macroblocks may be regenerated according to a concealment strategy if a syntax error is found within the current image slice.

Abstract translation: 一种用于检测包括图像帧序列的数字视频信号中的错误的方法和装置，每个图像帧包括一系列图像片段，每个图像片段包括宏块序列，每个宏块包括多个像素。 宏块解码器包括错误检测单元，其操作以计算当前宏块和一个或多个相邻宏块之间的边界的至少一部分上的像素值之间的误差度量，并且如果误差度量大于当前宏块，则将当前宏块标记为可疑 阈值水平。 根据来自一个或多个先前图像帧的加权平均误差度量来调整阈值电平。 如果在当前图像切片内发现语法错误，则可以根据隐藏策略重新生成可疑宏块和随后的帧间编码宏块。