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    HIGH RESISTIVITY SILICON-ON-INSULATOR SUBSTRATE AND METHOD OF FORMING
    102.
    发明申请
    HIGH RESISTIVITY SILICON-ON-INSULATOR SUBSTRATE AND METHOD OF FORMING 有权
    高电阻率绝缘子基板及其形成方法

    公开(公告)号：US20130168835A1

    公开(公告)日：2013-07-04

    申请号：US13342697

    申请日：2012-01-03

    Applicant: Alan B. Botula ,  Mark D. Jaffe ,  Alvin J. Joseph

    Inventor： Alan B. Botula ,  Mark D. Jaffe ,  Alvin J. Joseph

    IPC: H01L23/58 ,  H01L21/762

    CPC classification number: H01L29/16 ,  H01L21/76254

    Abstract: A semiconductor structure and a method of forming the same. In one embodiment, a method of forming a silicon-on-insulator (SOI) wafer substrate includes: providing a handle substrate; forming a high resistivity material layer over the handle substrate, the high resistivity material layer including one of an amorphous silicon carbide (SiC), a polycrystalline SiC, an amorphous diamond, or a polycrystalline diamond; forming an insulator layer over the high resistivity material layer; and bonding a donor wafer to a top surface of the insulator layer to form the SOI wafer substrate.

    Abstract translation: 半导体结构及其形成方法。 在一个实施例中，形成绝缘体上硅（SOI）晶片衬底的方法包括：提供处理衬底; 在所述手柄衬底上形成高电阻率材料层，所述高电阻率材料层包括非晶碳化硅（SiC），多晶SiC，无定形金刚石或多晶金刚石中的一种; 在所述高电阻率材料层上形成绝缘体层; 并将施主晶片接合到绝缘体层的顶表面以形成SOI晶片衬底。

    Methods of forming silicide strapping in imager transfer gate device
    105.
    发明授权
    Methods of forming silicide strapping in imager transfer gate device 有权
    在成像器传输门装置中形成硅化物带的方法

    公开(公告)号：US08158453B2

    公开(公告)日：2012-04-17

    申请号：US12699419

    申请日：2010-02-03

    Applicant: James W. Adkisson ,  John J. Ellis-Monaghan ,  R. Michael Guidash ,  Mark D. Jaffe ,  Edward T. Nelson ,  Richard J. Rassel ,  Charles V. Stancampiano

    Inventor： James W. Adkisson ,  John J. Ellis-Monaghan ,  R. Michael Guidash ,  Mark D. Jaffe ,  Edward T. Nelson ,  Richard J. Rassel ,  Charles V. Stancampiano

    IPC: H01L21/336

    CPC classification number: H01L27/14609 ,  H01L27/14643 ,  H01L27/14689

    Abstract: A CMOS active pixel sensor (APS) cell structure having dual workfunction transfer gate device and method of fabrication. The transfer gate device comprises a dielectric layer formed on a substrate and a dual workfunction gate conductor layer formed on the dielectric layer comprising a first conductivity type doped region and an abutting second conductivity type doped region. The transfer gate device defines a channel region where charge accumulated by a photosensing device is transferred to a diffusion region. A silicide structure is formed atop the dual workfunction gate conductor layer for electrically coupling the first and second conductivity type doped regions. In one embodiment, the silicide contact is smaller in area dimension than an area dimension of said dual workfunction gate conductor layer. Presence of the silicide strap prevents the diodic behavior from allowing one or the other side of the gate to float to an indeterminate voltage.

    Abstract translation: 具有双功能转移栅极器件和制造方法的CMOS有源像素传感器（APS）单元结构。 传输栅极器件包括形成在衬底上的电介质层和形成在包括第一导电类型掺杂区和邻接第二导电类型掺杂区的电介质层上的双功函数栅导体层。 传输门装置限定了由光敏装置累积的电荷被传送到扩散区的沟道区。 在双功函数栅极导体层顶部形成硅化物结构，用于电耦合第一和第二导电类型掺杂区域。 在一个实施例中，硅化物接触面积尺寸小于所述双功函数栅极导体层的面积尺寸。 硅化物带的存在防止了双极性行为允许栅极的一侧或另一侧浮动到不确定的电压。

    Isolation with offset deep well implants
    107.
    发明授权
    Isolation with offset deep well implants 有权
    隔离与偏移深井植入物

    公开(公告)号：US08034699B2

    公开(公告)日：2011-10-11

    申请号：US12464206

    申请日：2009-05-12

    Applicant: James W. Adkisson ,  Andres Bryant ,  Mark D. Jaffe ,  Alain Loiseau

    Inventor： James W. Adkisson ,  Andres Bryant ,  Mark D. Jaffe ,  Alain Loiseau

    IPC: H01L21/425

    CPC classification number: H01L29/1083 ,  H01L21/26513 ,  H01L21/823892

    Abstract: A method implants impurities into well regions of transistors. The method prepares a first mask over a substrate and performs a first shallow well implant through the first mask to implant first-type impurities to a first depth of the substrate. The first mask is removed and a second mask is prepared over the substrate. The method performs a second shallow well implant through the second mask to implant second-type impurities to the first depth of the substrate and then removes the second mask. A third mask is prepared over the substrate. The third mask has openings smaller than openings in the first mask and the second mask. A first deep well implant is performed through the third mask to implant the first-type impurities to a second depth of the substrate, the second depth of the substrate being greater than the first depth of the substrate. The third mask is removed and a fourth mask is prepared over the substrate, the fourth mask has openings smaller than the openings in the first mask and the second mask. Then, a second deep well implant is performed through the fourth mask to implant the second-type impurities to the second depth of the substrate.

    Abstract translation: 一种方法是将杂质掺入晶体管的阱区。 该方法在衬底上制备第一掩模，并且通过第一掩模执行第一浅阱注入，以将第一类型杂质注入到衬底的第一深度。 去除第一个掩模，并在衬底上制备第二个掩模。 该方法通过第二掩模执行第二浅井注入，以将第二类型杂质植入衬底的第一深度，然后移除第二掩模。 在衬底上制备第三个掩模。 第三掩模具有比第一掩模和第二掩模中的开口小的开口。 通过第三掩模执行第一深孔注入，以将第一类型的杂质注入衬底的第二深度，衬底的第二深度大于衬底的第一深度。 去除第三掩模并在衬底上制备第四掩模，第四掩模具有小于第一掩模和第二掩模中的开口的开口。 然后，通过第四掩模进行第二深孔注入，以将第二类型的杂质植入到衬底的第二深度。

    Image sensor monitor structure in scribe area
    109.
    发明授权
    Image sensor monitor structure in scribe area 失效
    图像传感器监控结构在划片区域

    公开(公告)号：US07915056B2

    公开(公告)日：2011-03-29

    申请号：US12051868

    申请日：2008-03-20

    Applicant: John J. Ellis-Monaghan ,  Mark D. Jaffe ,  Sambasivan Narayan ,  Anthony J. Perri ,  Richard J. Rassel ,  Tian Xia

    Inventor： John J. Ellis-Monaghan ,  Mark D. Jaffe ,  Sambasivan Narayan ,  Anthony J. Perri ,  Richard J. Rassel ,  Tian Xia

    IPC: G01R31/26

    CPC classification number: H01L22/34 ,  G01R31/2884 ,  H01L2924/0002 ,  H01L2924/00

    Abstract: A semiconductor die including a semiconductor chip and a test structure, located in a scribe area, is designed and manufactured. The test structure includes an array of complementary metal oxide semiconductor (CMOS) image sensors that are of the same type as CMOS image sensors employed in another array in the semiconductor chip and having a larger array size. Such a test structure is provided in a design phase by providing a design structure in which the orientations of the CMOS image sensors match between the two arrays. The test structure provides effective and accurate monitoring of manufacturing processes through in-line testing before a final test on the semiconductor chip.

    Abstract translation: 设计并制造了包括位于划线区域中的半导体芯片和测试结构的半导体管芯。 测试结构包括互补金属氧化物半导体（CMOS）图像传感器的阵列，其与在半导体芯片中的另一阵列中使用并具有较大阵列尺寸的CMOS图像传感器具有相同的类型。 通过提供CMOS图像传感器的取向在两个阵列之间匹配的设计结构，在设计阶段提供了这种测试结构。 测试结构通过在半导体芯片上的最终测试之前的在线测试来提供对制造工艺的有效和准确的监控。

    Pixel array, imaging sensor including the pixel array and digital camera including the imaging sensor
    110.
    发明授权
    Pixel array, imaging sensor including the pixel array and digital camera including the imaging sensor 有权
    像素阵列，包括像素阵列的成像传感器和包括成像传感器的数码相机

    公开(公告)号：US07821553B2

    公开(公告)日：2010-10-26

    申请号：US11275417

    申请日：2005-12-30

    Applicant: John J. Ellis-Monaghan ,  Mark D. Jaffe ,  Alain Loiseau ,  Richard J. Rassel

    Inventor： John J. Ellis-Monaghan ,  Mark D. Jaffe ,  Alain Loiseau ,  Richard J. Rassel

    IPC: H04N3/14 ,  H04N5/335 ,  H04N9/04 ,  H04N9/083

    CPC classification number: H04N9/045

    Abstract: A pixel array in an image sensor, the image sensor and a digital camera including the image sensor. The image sensor includes a pixel array with colored pixels and unfiltered (color filter-free) pixels. Each unfiltered pixel occupies one or more array locations. The colored pixels may be arranged in uninterrupted rows and columns with unfiltered pixels disposed between the uninterrupted rows and columns. The image sensor may in CMOS with the unfiltered pixels reducing low-light noise and improving low-light sensitivity.

    Abstract translation: 图像传感器中的像素阵列，图像传感器和包括图像传感器的数字照相机。 图像传感器包括具有彩色像素和未滤波（无滤色器）像素的像素阵列。 每个未过滤的像素占据一个或多个阵列位置。 彩色像素可以布置在不间断的行和列中，其中未过滤的像素布置在不间断的行和列之间。 图像传感器可以在CMOS中，未滤色像素降低低光噪声并改善低光灵敏度。

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