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36 条记录 (耗时 0.025 秒)

    Electrical Transmission Line Repair Device
    1.
    发明申请
    Electrical Transmission Line Repair Device 有权
    电力线路维修装置

    公开(公告)号：US20160104954A1

    公开(公告)日：2016-04-14

    申请号：US14514318

    申请日：2014-10-14

    申请人： Randy L. Wolf ,  Carl Russel Tamm

    发明人： Randy L. Wolf ,  Carl Russel Tamm

    IPC分类号： H01R4/44 ,  H01R4/62

    CPC分类号： H01R43/002 ,  H01B9/008 ,  H01R4/366 ,  H01R4/44 ,  H01R4/62 ,  H01R13/53 ,  H02G1/02

    摘要： An electrical transmission line repair device including a first conductor clamp, a second conductor clamp and at least one tie rail extending between the first and second conductor clamps in a spaced apart orientation. The first conductor clamp including a lower assembly and an upper assembly. The lower assembly and the upper assembly are slidably engageable with each other so as to define a conductor cavity extending therealong. Clamping fasteners are configured to extend through openings in the upper assembly so as to be threadable toward and away from the conductor contact region of the lower assembly within the conductor cavity.

    摘要翻译： 一种电传输线修复装置，包括第一导体夹，第二导体夹和至少一个连接导轨，其以间隔开的方向在第一和第二导体夹之间延伸。 第一导体夹具包括下部组件和上部组件。 下部组件和上部组件可滑动地彼此接合，以便限定沿其延伸的导体腔。 夹紧紧固件被构造成延伸穿过上部组件中的开口，以便能够朝向和远离导体腔内的下部组件的导体接触区域而被螺纹连接。

    POWER AMPLIFICATION OF A MULTI-TONE TEST SIGNAL
    3.
    发明申请
    POWER AMPLIFICATION OF A MULTI-TONE TEST SIGNAL 有权
    多音测试信号的功率放大

    公开(公告)号：US20130320995A1

    公开(公告)日：2013-12-05

    申请号：US13485872

    申请日：2012-05-31

    申请人： Randy L. Wolf

    发明人： Randy L. Wolf

    IPC分类号： G01R27/28 ,  H03F1/26

    CPC分类号： G01R27/28 ,  G01R31/2841

    摘要： Disclosed are a circuit and method for amplifying the power of a multi-tone input signal. The multi-tone input signal is filtered separating out one signal having a tone at a fundamental frequency from another signal having additional tones at additional frequencies. The signal having the tone at the fundamental frequency is amplified and then filtered removing any harmonics added during amplification. The signals are then recombined generating a multi-tone output signal, wherein the tone at the fundamental frequency is boosted (i.e., has a higher power in the multi-tone output signal than in the multi-tone input signal), but the additional tones at the additional frequencies are not (i.e., the additional tones at the additional frequencies have essentially the same power in the multi-tone output and input signals). Also disclosed herein are embodiments of a testing system and method incorporating the above-described circuit to allow for testing of high power devices.

    摘要翻译： 公开了用于放大多音调输入信号的功率的电路和方法。 对多音调输入信号进行滤波，从具有附加频率的附加音调的另一信号中分离出具有基频的音调的一个信号。 在基频处具有音调的信号被放大，然后滤除去放大期间加入的任何谐波。 然后，重新组合信号以产生多音调输出信号，其中基频处的音调被提升（​​即，在多音调输出信号中具有比在多音调输入信号中更高的功率），但附加音调 在附加频率处不是（即，附加频率处的附加音调在多音调输出和输入信号中具有基本上相同的功率）。 本文还公开了包含上述电路以允许测试高功率器件的测试系统和方法的实施例。

    Semiconductor-on-insulator substrate and structure including multiple order radio frequency harmonic supressing region
    6.
    发明授权
    Semiconductor-on-insulator substrate and structure including multiple order radio frequency harmonic supressing region 有权
    绝缘体上半导体基板和结构包括多阶射频谐波抑制区域

    公开(公告)号：US08299537B2

    公开(公告)日：2012-10-30

    申请号：US12369099

    申请日：2009-02-11

    申请人： Joseph R. Greco ,  Kevin Munger ,  Richard A. Phelps ,  Jennifer C. Robbins ,  William Savaria ,  James A. Slinkman ,  Randy L. Wolf

    发明人： Joseph R. Greco ,  Kevin Munger ,  Richard A. Phelps ,  Jennifer C. Robbins ,  William Savaria ,  James A. Slinkman ,  Randy L. Wolf

    IPC分类号： H01L21/70

    CPC分类号： H01L21/7624 ,  H01L21/26506 ,  H01L21/84 ,  H01L27/1203

    摘要： A semiconductor-on-insulator substrate and a related semiconductor structure, as well as a method for fabricating the semiconductor-on-insulator substrate and the related semiconductor structure, provide for a multiple order radio frequency harmonic suppressing region located and formed within a base semiconductor substrate at a location beneath an interface of a buried dielectric layer with the base semiconductor substrate within the semiconductor-on-insulator substrate. The multiple order radio frequency harmonic suppressing region may comprise an ion implanted atom, such as but not limited to a noble gas atom, to provide a suppressed multiple order radio frequency harmonic when powering a radio frequency device, such as but not limited to a radio frequency complementary metal oxide semiconductor device (or alternatively a passive device), located and formed within and upon a surface semiconductor layer within the semiconductor structure.

    摘要翻译： 绝缘体上半导体衬底和相关半导体结构以及绝缘体上半导体衬底和相关半导体结构的制造方法提供了一种位于并形成在基底半导体内的多阶射频谐波抑制区域 在绝缘体上半导体衬底内的掩埋介质层与基底半导体衬底的界面下方的位置处的衬底。 多级射频谐波抑制区域可以包括离子注入原子，例如但不限于稀有气体原子，以在对射频设备供电时提供抑制的多阶射频谐波，例如但不限于无线电 位于和形成在半导体结构内的表面半导体层内和之上的高频互补金属氧化物半导体器件（或替代地，无源器件）。

    SILICON-ON-INSULATOR (SOI) STRUCTURE CONFIGURED FOR REDUCED HARMONICS AND METHOD OF FORMING THE STRUCTURE
    7.
    发明申请
    SILICON-ON-INSULATOR (SOI) STRUCTURE CONFIGURED FOR REDUCED HARMONICS AND METHOD OF FORMING THE STRUCTURE 有权
    用于减少谐波的硅绝缘体（SOI）结构和形成结构的方法

    公开(公告)号：US20110127529A1

    公开(公告)日：2011-06-02

    申请号：US12627343

    申请日：2009-11-30

    申请人： Alan B. Botula ,  John J. Ellis-Monaghan ,  Alvin J. Joseph ,  Max G. Levy ,  Richard A. Phelps ,  James A. Slinkman ,  Randy L. Wolf

    发明人： Alan B. Botula ,  John J. Ellis-Monaghan ,  Alvin J. Joseph ,  Max G. Levy ,  Richard A. Phelps ,  James A. Slinkman ,  Randy L. Wolf

    IPC分类号： H01L27/12 ,  H01L21/762

    CPC分类号： H01L21/02488 ,  H01L21/2652 ,  H01L21/7624 ,  H01L21/84 ,  H01L27/1203 ,  H01L29/78603

    摘要： Disclosed is semiconductor structure with an insulator layer on a semiconductor substrate and a device layer is on the insulator layer. The substrate is doped with a relatively low dose of a dopant having a given conductivity type such that it has a relatively high resistivity. Additionally, a portion of the semiconductor substrate immediately adjacent to the insulator layer can be doped with a slightly higher dose of the same dopant, a different dopant having the same conductivity type or a combination thereof. Optionally, micro-cavities are created within this same portion so as to balance out any increase in conductivity due to increased doping with a corresponding increase in resistivity. Increasing the dopant concentration at the semiconductor substrate-insulator layer interface raises the threshold voltage (Vt) of any resulting parasitic capacitors and, thereby reduces harmonic behavior. Also disclosed herein are embodiments of a method for forming such a semiconductor structure.

    摘要翻译： 公开了在半导体衬底上具有绝缘体层并且器件层位于绝缘体层上的半导体结构。 衬底掺杂有相对低剂量的具有给定导电类型的掺杂剂，使得其具有相对高的电阻率。 此外，与绝缘体层紧密相邻的半导体衬底的一部分可掺杂略高的相同掺杂剂剂量，具有相同导电类型的不同掺杂剂或其组合。 可选地，在该相同部分内形成微腔，以便平衡由于掺杂增加导致的电导率的增加，同时具有相应的电阻率增加。 增加半导体衬底 - 绝缘体层界面处的掺杂剂浓度会提高任何结果的寄生电容器的阈值电压（Vt），从而降低谐波行为。 本文还公开了用于形成这种半导体结构的方法的实施例。

    Electrical transmission line repair device
    8.
    发明授权
    Electrical transmission line repair device 有权
    电力线路维修装置

    公开(公告)号：US09577354B2

    公开(公告)日：2017-02-21

    申请号：US14514318

    申请日：2014-10-14

    申请人： Randy L. Wolf ,  Carl Russel Tamm

    发明人： Randy L. Wolf ,  Carl Russel Tamm

    IPC分类号： H01R4/44 ,  H01R43/00 ,  H01R4/36 ,  H01R13/53 ,  H02G1/02 ,  H01R11/07 ,  H01R4/62

    CPC分类号： H01R43/002 ,  H01B9/008 ,  H01R4/366 ,  H01R4/44 ,  H01R4/62 ,  H01R13/53 ,  H02G1/02

    摘要： An electrical transmission line repair device including a first conductor clamp, a second conductor clamp and at least one tie rail extending between the first and second conductor clamps in a spaced apart orientation. The first conductor clamp including a lower assembly and an upper assembly. The lower assembly and the upper assembly are slidably engageable with each other so as to define a conductor cavity extending therealong. Clamping fasteners are configured to extend through openings in the upper assembly so as to be threadable toward and away from the conductor contact region of the lower assembly within the conductor cavity.

    摘要翻译： 一种电传输线修复装置，包括第一导体夹，第二导体夹和至少一个连接导轨，其以间隔开的方向在第一和第二导体夹之间延伸。 第一导体夹具包括下部组件和上部组件。 下部组件和上部组件可滑动地彼此接合，以便限定沿其延伸的导体腔。 夹紧紧固件被构造成延伸穿过上部组件中的开口，以便能够朝向和远离导体腔内的下部组件的导体接触区域而被螺纹连接。

    Method, apparatus, and design structure for silicon-on-insulator high-bandwidth circuitry with reduced charge layer
    10.
    发明授权
    Method, apparatus, and design structure for silicon-on-insulator high-bandwidth circuitry with reduced charge layer 有权
    具有降低电荷层的绝缘体上硅高带宽电路的方法，设备和设计结构

    公开(公告)号：US08492868B2

    公开(公告)日：2013-07-23

    申请号：US12848558

    申请日：2010-08-02

    申请人： Alan B. Botula ,  Alvin J. Joseph ,  James A. Slinkman ,  Randy L. Wolf

    发明人： Alan B. Botula ,  Alvin J. Joseph ,  James A. Slinkman ,  Randy L. Wolf

    IPC分类号： H01L29/06 ,  H01L21/762

    CPC分类号： H01L21/76283 ,  H01L21/84 ,  H01L27/0211 ,  H01L27/0617 ,  H01L27/1203

    摘要： A method, integrated circuit and design structure includes a silicon substrate layer having trench structures and an ion impurity implant. An insulator layer is positioned on and contacts the silicon substrate layer. The insulator layer fills the trench structures. A circuitry layer is positioned on and contacts the buried insulator layer. The circuitry layer comprises groups of active circuits separated by passive structures. The trench structures are positioned between the groups of active circuits when the integrated circuit structure is viewed from the top view. Thus, the trench structures are below the passive structures and are not below the groups of circuits when the integrated circuit structure is viewed from the top view.

    摘要翻译： 一种方法，集成电路和设计结构包括具有沟槽结构的硅衬底层和离子杂质植入物。 绝缘体层位于硅衬底层上并接触硅衬底层。 绝缘体层填充沟槽结构。 电路层位于掩埋绝缘体层上并与其接触。 电路层包括由被动结构分开的一组有源电路。 当从顶视图观察集成电路结构时，沟槽结构位于有源电路组之间。 因此，当从顶视图观察集成电路结构时，沟槽结构在被动结构之下并且不在电路组下方。