公开(公告)号：US11894077B2

公开(公告)日：2024-02-06

申请号：US17678584

申请日：2022-02-23

Applicant: SanDisk Technologies LLC

Inventor： Ke Zhang ,  Minna Li ,  Liang Li

IPC: G11C16/34 ,  G11C16/10 ,  G11C16/30 ,  G11C16/08 ,  G11C16/26

CPC classification number: G11C16/3459 ,  G11C16/08 ,  G11C16/102 ,  G11C16/26 ,  G11C16/30

Abstract: A memory apparatus and operating method are provided. The apparatus includes memory cells connected to word lines and disposed in memory holes and configured to retain a threshold voltage. The memory holes are organized in rows grouped in strings. A control means is coupled to the word lines and the memory holes and programs the memory cells associated with a first one of the strings in a program operation and acquire a smart verify programming voltage in a smart verify operation including smart verify loops. The control means discards the smart verify programming voltage and determines another smart verify programming voltage in another smart verify operation on the memory cells associated with a second one of the strings in response to a quantity of the smart verify loops needed to complete programming of the memory cells associated with the first one of the strings being outside a predetermined threshold criteria.

公开(公告)号：US11894064B2

公开(公告)日：2024-02-06

申请号：US17583570

申请日：2022-01-25

Applicant: SanDisk Technologies LLC

Inventor： Xiang Yang

IPC: G11C16/16 ,  G11C16/26 ,  G11C16/10 ,  G11C16/04

CPC classification number: G11C16/16 ,  G11C16/0483 ,  G11C16/102 ,  G11C16/26

Abstract: The memory device includes a block with a plurality of memory cells arranged in a plurality of data word lines, which are arranged in sub-blocks that are not separated from one another by physical joints or by dummy word lines. A controller is configured to erase the memory cells of a selected sub-block of the plurality of sub-blocks without erasing the memory cells of the unselected sub-blocks. The controller reads data of the edge one word lines of the unselected sub-blocks adjacent the selected sub-block and stores this data in a temporary location external of the block before erasing the memory cells of the selected sub-block. The controller then re-programs the data that is being temporarily stored back into the memory cells of the edge word lines of the unselected sub-blocks after erase of the selected sub-block is completed.

公开(公告)号：US20240040786A1

公开(公告)日：2024-02-01

申请号：US18484156

申请日：2023-10-10

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Yusuke YOSHIDA ,  Teruo OKINA ,  Takanori HANADA ,  Shigeyuki YOSHIDA

IPC: H10B43/27 ,  H10B41/27

CPC classification number: H10B43/27 ,  H10B41/27

Abstract: A semiconductor structure includes an alternating stack of insulating layers and electrically conductive layers that is located on a front side of at least one semiconductor material layer. memory openings vertically extending through the alternating stack, memory opening fill structures located in the memory openings and including a respective vertical semiconductor channel and a respective vertical stack of memory elements, a dielectric material portion laterally offset from the alternating stack, a connection via structure vertically extending through the dielectric material portion, a metallic plate in contact with a proximal end surface of the connection via structure, and a backside contact pad in electrical contact with the metallic plate and spaced from the connection via structure by the metallic plate.

公开(公告)号：US20240036740A1

公开(公告)日：2024-02-01

申请号：US17983870

申请日：2022-11-09

Applicant: SanDisk Technologies LLC

Inventor： Yihang Liu ,  Xiaochen Zhu ,  Jie Liu ,  Sarath Puthenthermadam ,  Jiahui Yuan ,  Feng Gao

IPC: G06F3/06

CPC classification number: G06F3/0619 ,  G06F3/064 ,  G06F3/0679

Abstract: A non-volatile memory system separately performs a memory operation for multiple sub-blocks of a block in order from previously determined slowest sub-block of the block to a previously determined faster sub-block of the block. As a slower sub-block is more likely to fail, this order of is more likely to identify a failure earlier in the process thereby saving time and reducing potential for a disturb. In some embodiments, the proposed order of operation can be used in conjunction with a programming process that concurrently programs blocks in multiple planes using completion of programming of a fastest plane to a data state as a trigger to test for program failure of other planes to the data state.

公开(公告)号：US11889684B2

公开(公告)日：2024-01-30

申请号：US16951325

申请日：2020-11-18

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Masanori Tsutsumi ,  Shinsuke Yada ,  Mitsuteru Mushiga ,  Akio Nishida ,  Hiroyuki Ogawa ,  Teruo Okina

IPC: H10B41/27 ,  H01L29/06 ,  G11C7/18 ,  G11C8/14 ,  H10B41/10 ,  H10B41/35 ,  H10B43/10 ,  H10B43/27 ,  H10B43/35

CPC classification number: H10B41/27 ,  G11C7/18 ,  G11C8/14 ,  H01L29/0653 ,  H10B41/10 ,  H10B41/35 ,  H10B43/10 ,  H10B43/27 ,  H10B43/35

Abstract: A three-dimensional memory device includes an alternating stack of insulating layers and electrically conductive layers located over at least one source layer, and groups of memory opening fill structures vertically extending through the alternating stack. Each memory opening fill structure can include a vertical stack of memory elements and a vertical semiconductor channel. A plurality of source-side select gate electrodes can be laterally spaced apart by source-select-level dielectric isolation structures. Alternatively or additionally, the at least one source layer may include a plurality of source layers. A group of memory opening fill structures can be selected by selecting a source layer and/or by selecting a source-level electrically conductive layer.

公开(公告)号：US11887674B2

公开(公告)日：2024-01-30

申请号：US17706993

申请日：2022-03-29

Applicant: SanDisk Technologies LLC

Inventor： Yanjie Wang ,  Guirong Liang ,  Xiaoyu Che ,  Yi Song

IPC: G11C11/34 ,  G11C16/26 ,  G11C16/04 ,  G11C11/56 ,  G11C16/24 ,  G11C16/32 ,  G11C16/08

CPC classification number: G11C16/26 ,  G11C11/5642 ,  G11C16/0483 ,  G11C16/08 ,  G11C16/24 ,  G11C16/32

Abstract: A memory apparatus and method of operation is provided. The apparatus includes memory cells each connected to one of a plurality of word lines. The memory cells are disposed in strings coupled to one of a plurality of bit lines and are configured to retain a threshold voltage corresponding to one of a plurality of data states. A control means is configured to read each of the memory cells in a read operation. For each one of the memory cells, the control means is also configured to offset at least one of a bit line settling time and a kick voltage during the read operation based on a probability of at least one neighboring one of the plurality of bit lines being coupled to the memory cells retaining the threshold voltage corresponding to a different one of the plurality of data states than the one of the memory cells.

公开(公告)号：US20240029806A1

公开(公告)日：2024-01-25

申请号：US17872148

申请日：2022-07-25

Applicant: SanDisk Technologies LLC

Inventor： Jiacen Guo ,  Peng Zhang ,  Xiang Yang ,  Yanli Zhang

IPC: G11C16/34 ,  G11C16/10 ,  G11C16/08 ,  G11C16/24 ,  G11C16/04

CPC classification number: G11C16/3459 ,  G11C16/102 ,  G11C16/08 ,  G11C16/24 ,  G11C16/0483

Abstract: In a non-volatile memory system that performs programming of selected memory cells (in coordination with pre-charging and boosting of channels for unselected memory cells) and program-verify to determine whether the programming was successful, the system transitions from program-verify to the next dose of programming by concurrently lowering a voltage applied to a selected word line and voltages applied to word lines on a first side of the selected word line at the conclusion of program-verify. Subsequent to lowering the voltage applied to the selected word line, the system successively lowers voltages applied to groups of one or more word lines on a second side of the selected word line at the conclusion of program-verify beginning with a group of one or more word lines immediately adjacent the selected word line and progressing to other groups of one or more word lines disposed increasingly remote from the selected word line.

公开(公告)号：US20240015963A1

公开(公告)日：2024-01-11

申请号：US17811145

申请日：2022-07-07

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Tadashi NAKAMURA ,  Nobuyuki FUJIMURA

IPC: H01L27/11582 ,  H01L27/11556

CPC classification number: H01L27/11582 ,  H01L27/11556

Abstract: A semiconductor structure includes an alternating stack of insulating layers and electrically conductive layers, where the electrically conductive layers include word line electrically conductive layers and a first select-level electrically conductive layer, a memory opening vertically extending through the alternating stack, and a memory opening fill structure located in the memory opening and including a memory film and a vertical semiconductor channel. A vertical cross-sectional profile of an outer sidewall of the vertical semiconductor channel is straight throughout the word line electrically conductive layers and contains a lateral protrusion at a level of the first select-level electrically conductive layer.

公开(公告)号：US11862260B2

公开(公告)日：2024-01-02

申请号：US17671015

申请日：2022-02-14

Applicant: SanDisk Technologies LLC

Inventor： Jiacen Guo ,  Swaroop Kaza

IPC: G11C16/34 ,  G11C16/04 ,  G11C16/08 ,  G11C16/16 ,  H10B43/27

CPC classification number: G11C16/349 ,  G11C16/0483 ,  G11C16/08 ,  G11C16/16 ,  G11C16/3422 ,  H10B43/27

Abstract: Read disturb audit techniques that include algorithmically applying audit verify voltages to erased wordlines in an open memory block are described. In an audit verify technique, a pass-through voltage ensured to be higher than any threshold voltage of any cell is applied to each wordline in an open memory block that includes one or more programmed memory cells, and an audit verify voltage lower than the pass-through voltage is applied to each erased wordline. A first bit count representing a number of non-conductive bitline(s) is determined and compared to a threshold value to determine whether to continue or discontinue block operation. In an audit verify and audit gap technique, the erased wordlines are divided into disjoint first and second groups, and an audit verify voltage and a non-verify voltage are alternatively applied to the groups in different audit verify stages.

公开(公告)号：US11856765B2

公开(公告)日：2023-12-26

申请号：US17317578

申请日：2021-05-11

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Koichi Matsuno ,  Masaaki Higashitani ,  Johann Alsmeier

IPC: H01L27/11582 ,  H10B41/27 ,  H10B41/10 ,  H10B41/35 ,  H10B43/10 ,  H10B43/27 ,  H10B43/35

CPC classification number: H10B41/27 ,  H10B41/10 ,  H10B41/35 ,  H10B43/10 ,  H10B43/27 ,  H10B43/35

Abstract: A three-dimensional memory device includes an alternating stack of insulating layers and electrically conductive layers located over a substrate, an array of memory opening fill structures located within an array of memory openings vertically extending through the alternating stack, and a drain-select-level isolation structure vertically extending through drain-select-level electrically conductive layers between two rows of memory opening fill structures. The drain-select-level isolation structure may comprise a low-k dielectric material or an air gap.