公开(公告)号：US07871860B1

公开(公告)日：2011-01-18

申请号：US12620321

申请日：2009-11-17

申请人： Han-Ping Pu ,  Tsung-Shu Lin ,  Chen-Shien Chen

发明人： Han-Ping Pu ,  Tsung-Shu Lin ,  Chen-Shien Chen

IPC分类号： H01L21/00 ,  H01L21/50 ,  H01L21/48 ,  H01L21/44 ,  H01L21/46

CPC分类号： H01L24/81 ,  H01L21/563 ,  H01L24/16 ,  H01L2224/73203 ,  H01L2224/81211 ,  H01L2224/81801 ,  H01L2924/01006 ,  H01L2924/01019 ,  H01L2924/01032 ,  H01L2924/01033 ,  H01L2924/01049 ,  H01L2924/0105 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/1305 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/19041 ,  H01L2924/19042 ,  H01L2924/19043 ,  H01L2924/351 ,  H01L2924/00

摘要： The present disclosure provides a method of fabricating a semiconductor device. The method includes providing a chip and a substrate. The method also includes bonding the chip to the substrate. The method also includes, after the bonding the chip, dispensing a sealing material between the chip and the substrate. In accordance with the method, the chip and the substrate are maintained within a temperature range from the bonding the chip to the dispensing the sealing material, and wherein a lower limit of the temperature range is approximately twice a room temperature.

摘要翻译： 本公开提供了制造半导体器件的方法。 该方法包括提供芯片和基板。 该方法还包括将芯片接合到衬底。 该方法还包括在粘合芯片之后，在芯片和基板之间分配密封材料。 根据该方法，将芯片和基板保持在从接合芯片到分配密封材料的温度范围内，并且其中温度范围的下限约为室温的两倍。

公开(公告)号：US20090020864A1

公开(公告)日：2009-01-22

申请号：US11779192

申请日：2007-07-17

申请人： Han-Ping Pu ,  Mirng-Ji Lii

发明人： Han-Ping Pu ,  Mirng-Ji Lii

IPC分类号： H01L23/22 ,  H01L21/00

CPC分类号： H01L21/568 ,  H01L21/561 ,  H01L21/6835 ,  H01L23/3107 ,  H01L24/13 ,  H01L24/19 ,  H01L24/96 ,  H01L24/97 ,  H01L2224/0401 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/13 ,  H01L2224/13099 ,  H01L2224/16 ,  H01L2224/20 ,  H01L2224/97 ,  H01L2924/00013 ,  H01L2924/01013 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01078 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2224/82 ,  H01L2224/29099 ,  H01L2924/00

摘要： A method of forming a package structure with reduced damage to semiconductor dies is provided. The method includes providing a die comprising bond pads on a top surface of the die; forming bumps on the bond pads of the die, wherein the bumps have top surfaces higher than the top surface of the die; mounting the die on a chip carrier, wherein the bumps are attached to the chip carrier; molding the die onto the chip carrier with a molding compound; de-mounting the chip carrier from the die; and forming redistribution traces over, and electrically connected to, the bumps of the die.

摘要翻译： 提供一种形成具有对半导体管芯的损伤减小的封装结构的方法。 所述方法包括提供在所述管芯的顶表面上包括接合焊盘的管芯; 在所述模具的接合焊盘上形成凸起，其中所述凸起具有高于所述模具的顶表面的顶表面; 将所述管芯安装在芯片载体上，其中所述凸块附接到所述芯片载体上; 用模塑料将模具成型到芯片载体上; 将芯片载体从芯片上拆下; 以及在模具的凸起上形成并电连接到模具的凸块上的再分布迹线。

公开(公告)号：US20080296764A1

公开(公告)日：2008-12-04

申请号：US11807522

申请日：2007-05-29

申请人： Kuo-Chin Chang ,  Han-Ping Pu ,  Pei-Haw Tsao

发明人： Kuo-Chin Chang ,  Han-Ping Pu ,  Pei-Haw Tsao

IPC分类号： H01L23/488 ,  H01L21/44

CPC分类号： H01L24/11 ,  H01L24/81 ,  H01L2224/0231 ,  H01L2224/0401 ,  H01L2224/114 ,  H01L2224/1147 ,  H01L2224/1148 ,  H01L2224/116 ,  H01L2224/11902 ,  H01L2224/13019 ,  H01L2224/13076 ,  H01L2224/13078 ,  H01L2224/13099 ,  H01L2224/131 ,  H01L2224/81801 ,  H01L2924/01004 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01015 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01075 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01327 ,  H01L2924/014 ,  H01L2924/14 ,  H01L2924/181 ,  H01L2924/00

摘要： An enhanced wafer level chip scale packaging (WLCSP) copper electrode post is described having one or more pins that protrude from the top of the electrode post. When the solder ball is soldered onto the post, the pins are encapsulated within the solder material. The pins not only add shear strength to the soldered joint between the solder ball and the electrode post but also create a more reliable electrical connection due to the increased surface area between the electrode post/pin combination and the solder ball. Moreover, creating an irregularly shaped solder joint retards the propagation of cracks that may form in the intermetal compounds (IMC) layer formed at the solder joint.

摘要翻译： 描述了增强的晶片级芯片级封装（WLCSP）铜电极柱，其具有从电极柱的顶部突出的一个或多个引脚。 当焊球焊接到柱上时，引脚被封装在焊料材料内。 引脚不仅在焊球和电极柱之间的焊接接头上增加剪切强度，而且由于电极柱/销组合和焊球之间的表面积增加，也产生更可靠的电连接。 此外，产生不规则形状的焊点阻碍了可能在焊接接头形成的金属间化合物（IMC）层中形成的裂纹的传播。

公开(公告)号：US20080286938A1

公开(公告)日：2008-11-20

申请号：US11798432

申请日：2007-05-14

申请人： Han-Ping Pu ,  Bai-Yao Lou ,  Dean Wang ,  Ching-Wen Hsiao ,  Kai-Ming Ching ,  Chen-Cheng Kuo ,  Wen-Chih Chiou ,  Ding-Chung Lu ,  Shang-Yun Hou

发明人： Han-Ping Pu ,  Bai-Yao Lou ,  Dean Wang ,  Ching-Wen Hsiao ,  Kai-Ming Ching ,  Chen-Cheng Kuo ,  Wen-Chih Chiou ,  Ding-Chung Lu ,  Shang-Yun Hou

IPC分类号： H01L21/30

CPC分类号： H01L21/78 ,  H01L2224/05001 ,  H01L2224/05022 ,  H01L2224/05023 ,  H01L2224/051 ,  H01L2224/05572 ,  H01L2224/056 ,  H01L2224/11 ,  H01L2924/00014

摘要： A method for packaging a semiconductor device disclosed. A substrate comprising a plurality of dies, separated by scribe line areas respectively is provided, wherein at least one layer is overlying the substrate. A portion of the layer within the scribe lines area is removed by photolithography and etching to form openings. The substrate is sawed along the scribe line areas, passing the openings. In alternative embodiment, a first substrate comprising a plurality of first dies separated by first scribe line areas respectively is provided, wherein at least one first structural layer is overlying the first substrate. The first structural layer is patterned to form first openings within the first scribe line areas. A second substrate comprising a plurality of second dies separated by second scribe line areas respectively is provided, wherein at least one second structural layer is overlying the substrate. The second structural layer is patterned to form second openings within the second scribe line areas. The first substrate and the second substrate are bonded to form a stack structure. The stack structure is cut along the first and second scribe line areas, passing the first and second openings.

摘要翻译： 一种封装半导体器件的方法。 提供了包括分别由划线区域分隔的多个管芯的衬底，其中至少一层覆盖衬底。 通过光刻和蚀刻去除划线部分内的层的一部分以形成开口。 沿着划线区域锯切基板，通过开口。 在替代实施例中，提供了包括分别由第一划线区域分开的多个第一裸片的第一衬底，其中至少一个第一结构层覆盖在第一衬底上。 图案化第一结构层以在第一划线区域内形成第一开口。 提供了包括分别由第二划线区域分隔的多个第二模具的第二衬底，其中至少一个第二结构层覆盖在衬底上。 图案化第二结构层以在第二划线区域内形成第二开口。 第一基板和第二基板被接合以形成堆叠结构。 沿着第一和第二划线区域切割堆叠结构，使第一和第二开口通过。

公开(公告)号：US20070249094A1

公开(公告)日：2007-10-25

申请号：US11820366

申请日：2007-06-19

申请人： Han-Ping Pu

发明人： Han-Ping Pu

IPC分类号： H01L21/50

CPC分类号： H05K1/141 ,  H01L24/97 ,  H01L25/03 ,  H01L25/0657 ,  H01L2224/0554 ,  H01L2224/0557 ,  H01L2224/05571 ,  H01L2224/05573 ,  H01L2224/16225 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/73253 ,  H01L2224/97 ,  H01L2225/06517 ,  H01L2225/06582 ,  H01L2225/06589 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01033 ,  H01L2924/01082 ,  H01L2924/15311 ,  H05K3/284 ,  H05K3/3436 ,  H05K2201/10515 ,  H05K2201/10674 ,  H05K2201/10689 ,  H01L2224/81 ,  H01L2224/05599 ,  H01L2224/0555 ,  H01L2224/0556

摘要： A multi-chip semiconductor package and a fabrication method thereof are provided. At least one first chip is mounted on and electrically connected to an upper surface of a substrate via solder bumps. A preformed package structure having a second chip and a first encapsulation body is mounted on the upper surface of the substrate, wherein outer leads of the preformed package structure are exposed from the first encapsulation body and electrically connected to the upper surface of the substrate. The first encapsulation body, outer leads and substrate form a space where the first chip is received, and a gap is present between the first chip and the first encapsulation body. A second encapsulation body is formed on the upper surface of the substrate to encapsulate the first chip, solder bumps and preformed package structure. A plurality of solder balls are implanted on the lower surface of the substrate.

摘要翻译： 提供一种多芯片半导体封装及其制造方法。 至少一个第一芯片通过焊料凸块安装在基板的上表面上并电连接到基板的上表面。 具有第二芯片和第一封装体的预制封装结构安装在基板的上表面上，其中预成型封装结构的外引线从第一封装体露出并电连接到基板的上表面。 第一封装体，外引线和衬底形成接收第一芯片的空间，并且在第一芯片和第一封装体之间存在间隙。 第二封装体形成在衬底的上表面上，以封装第一芯片，焊料凸块和预成型封装结构。 在基板的下表面上注入多个焊球。

公开(公告)号：US07057405B2

公开(公告)日：2006-06-06

申请号：US10757241

申请日：2004-01-14

申请人： Han-Ping Pu

发明人： Han-Ping Pu

IPC分类号： G01R31/02

CPC分类号： G01R31/2831

摘要： A wafer test method is performed for a wafer prior to forming bumps on the wafer, using a conductive interposer having one side with test pads and the other side with test bumps electrically connected to the test pads. The conductive interposer is mounted on the wafer having a plurality of chips, wherein the test bumps are in electrical contact with bond pads on active surfaces of the chips. Test probes are used to contact the test pads to perform tests for the chips. This wafer test method is beneficially performed prior to forming bumps on the wafer, such that the prior-art drawback of damaging bumps on the wafer by contacting test probes with the bumps on the wafer can be eliminated, and the conductive interposer mounted on the wafer prevents the test probes from physical contact with the bond pads on the chips, thereby not damaging the bond pads.

摘要翻译： 在晶片上形成凸块之前，使用具有一侧具有测试焊盘的导电插入件，另一侧具有电连接到测试焊盘的测试凸块，对晶片执行晶片测试方法。 导电插入件安装在具有多个芯片的晶片上，其中测试凸块与芯片的有效表面上的接合焊盘电接触。 测试探头用于与测试垫接触以对芯片进行测试。 在晶片上形成凸块之前有利地进行该晶片测试方法，从而可以消除通过使测试探针与晶片上的凸起接触而损坏晶片上的凸块的现有技术缺陷，并且安装在晶片上的导电插入器 防止测试探针与芯片上的接合焊盘物理接触，从而不损坏焊盘。

公开(公告)号：US20050212134A1

公开(公告)日：2005-09-29

申请号：US10921582

申请日：2004-08-18

申请人： Han-Ping Pu

发明人： Han-Ping Pu

IPC分类号： H01L21/60 ,  H01L23/04 ,  H01L23/64

CPC分类号： H01L24/81 ,  H01L23/642 ,  H01L2224/05571 ,  H01L2224/05573 ,  H01L2224/1403 ,  H01L2224/141 ,  H01L2224/16 ,  H01L2224/16225 ,  H01L2224/16265 ,  H01L2224/1703 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/81801 ,  H01L2224/92125 ,  H01L2924/00014 ,  H01L2924/01033 ,  H01L2924/014 ,  H01L2924/15311 ,  H01L2924/19041 ,  H01L2924/19043 ,  H01L2924/19103 ,  H01L2924/19104 ,  H01L2924/19105 ,  H01L2924/30105 ,  Y10S257/924 ,  H01L2924/00 ,  H01L2224/05599

摘要： A semiconductor package structure for improving electrical performance and a method for fabricating the same are proposed, in which a substrate having at least one pair of passive component pads is provided, wherein a semiconductor chip is attached on the substrate and a passive component is mounted to the passive component pads to locate between the substrate and the semiconductor chip. Thus, the passive component can electrically connect the chip and the substrate simultaneously without arranging an additional conductive trace layer, thereby improving the electrical performance of the semiconductor package structure and reducing the structure size.

摘要翻译： 提出了一种用于提高电性能的半导体封装结构及其制造方法，其中提供具有至少一对无源元件焊盘的衬底，其中半导体芯片附着在衬底上，并且将无源元件安装到 无源元件焊盘位于衬底和半导体芯片之间。 因此，无源部件可以同时电连接芯片和基板，而不需要设置附加的导电迹线层，从而提高半导体封装结构的电气性能并降低结构尺寸。

公开(公告)号：US20050007129A1

公开(公告)日：2005-01-13

申请号：US10757241

申请日：2004-01-14

申请人： Han-Ping Pu

发明人： Han-Ping Pu

IPC分类号： G01R31/28 ,  G01R31/02

CPC分类号： G01R31/2831

摘要： A wafer test method is performed for a wafer prior to forming bumps on the wafer, using a conductive interposer having one side with test pads and the other side with test bumps electrically connected to the test pads. The conductive interposer is mounted on the wafer having a plurality of chips, wherein the test bumps are in electrical contact with bond pads on active surfaces of the chips. Test probes are used to contact the test pads to perform tests for the chips. This wafer test method is beneficially performed prior to forming bumps on the wafer, such that the prior-art drawback of damaging bumps on the wafer by contacting test probes with the bumps on the wafer can be eliminated, and the conductive interposer mounted on the wafer prevents the test probes from physical contact with the bond pads on the chips, thereby not damaging the bond pads.

摘要翻译： 在晶片上形成凸块之前，使用具有一侧具有测试焊盘的导电插入件，另一侧具有电连接到测试焊盘的测试凸块，对晶片执行晶片测试方法。 导电插入件安装在具有多个芯片的晶片上，其中测试凸块与芯片的有效表面上的接合焊盘电接触。 测试探头用于与测试垫接触以对芯片进行测试。 在晶片上形成凸块之前有利地进行该晶片测试方法，从而可以消除通过使测试探针与晶片上的凸起接触而损坏晶片上的凸块的现有技术缺陷，并且安装在晶片上的导电插入器 防止测试探针与芯片上的接合焊盘物理接触，从而不损坏焊盘。

公开(公告)号：US06787918B1

公开(公告)日：2004-09-07

申请号：US09586525

申请日：2000-06-02

申请人： Ying-Chou Tsai ,  Han-Ping Pu ,  Shih-Kuang Chiu

发明人： Ying-Chou Tsai ,  Han-Ping Pu ,  Shih-Kuang Chiu

IPC分类号： H01L2348

CPC分类号： H01L23/49894 ,  H01L21/563 ,  H01L2224/05568 ,  H01L2224/05573 ,  H01L2224/056 ,  H01L2224/13021 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2224/73203 ,  H01L2224/73204 ,  H01L2924/01087 ,  H05K3/3436 ,  H05K3/3452 ,  H05K2201/094 ,  H05K2201/0989 ,  H05K2201/099 ,  H05K2201/10674 ,  H05K2201/10977 ,  H01L2924/00 ,  H01L2924/00014

摘要： A substrate structure of Flip Chip package includes a plurality of patterned circuit layers alternately stacking up with at least an insulative layer for isolating the patterned circuit layers. The patterned circuit layers are electrically connected each other wherein one of the patterned circuit layers is positioned on the surface of the substrate. The patterned circuit layer includes a plurality of first mounting pads and a plurality of second mounting pads. The solder mask layer covers the patterned circuit layer on the surface of the substrate, and a portion of the surface of the outer edge of the mounting pads while exposes a portion of the surface of the first mounting pads and the whole surface of the second mounting pads.

摘要翻译： 倒装芯片封装的衬底结构包括多个图案化电路层，其与至少一个用于隔离图案化电路层的绝缘层交替堆叠。 图案化电路层彼此电连接，其中一个图案化电路层位于衬底的表面上。 图案化电路层包括多个第一安装焊盘和多个第二安装焊盘。 焊接掩模层覆盖基板表面上的图案化电路层，并且安装焊盘的外边缘的表面的一部分暴露第一安装焊盘的表面的一部分和第二安装件的整个表面 垫

公开(公告)号：US06580618B2

公开(公告)日：2003-06-17

申请号：US09912276

申请日：2001-07-24

申请人： Han-Ping Pu

发明人： Han-Ping Pu

IPC分类号： H05K702

CPC分类号： H01L23/3128 ,  H01L24/48 ,  H01L25/0652 ,  H01L25/0657 ,  H01L2224/05599 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2224/32145 ,  H01L2224/45099 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73207 ,  H01L2224/85399 ,  H01L2924/00014 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2224/45015 ,  H01L2924/207 ,  H01L2924/00012

摘要： A low-profile multi-chip module is provided, wherein two or more chips are integrated in a package unit connected to a printed circuit board (PCB), to provide a manifold level of functionality and data storage capacity. The multi-chip module includes at least a first chip and a second chip connected to a predetermined position on an active surface of the first chip by chip-on-chip technology, allowing the active surface of the first chip to be further mounted to a substrate by flip-chip technology. The substrate is attached to the PCB by surface-mount technology, and interposed between the first chip and the PCB. At least a passive component is mounted on the PCB at a position beside the substrate and underneath the second chip. This structure allows the use of a PCB having a smaller layout area for implementing the multi-chip module, thereby desirably reducing the overall structural profile.

摘要翻译： 提供了一种低调多芯片模块，其中两个或更多个芯片集成在连接到印刷电路板（PCB）的封装单元中，以提供多功能级和数据存储容量。 多芯片模块包括至少第一芯片和第二芯片，其通过芯片上芯片技术连接到第一芯片的有源表面上的预定位置，从而允许第一芯片的有源表面进一步安装到 基板采用倒装芯片技术。 基板通过表面贴装技术连接到PCB，并插入在第一芯片和PCB之间。 至少一个无源元件安装在PCB上的位于基板旁边的第二芯片下方的位置。 该结构允许使用具有较小布局面积的PCB来实现多芯片模块，从而期望地减小整体结构轮廓。