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    Configuration of gate to drain (GD) clamp and ESD protection circuit for power device breakdown protection
    102.
    发明申请
    Configuration of gate to drain (GD) clamp and ESD protection circuit for power device breakdown protection 有权
    门极漏极（GD）钳位和ESD保护电路的配置用于电源器件击穿保护

    公开(公告)号：US20110151628A1

    公开(公告)日：2011-06-23

    申请号：US12932584

    申请日：2011-02-28

    申请人： Yi Su ,  Anup Bhalla ,  Daniel Ng

    发明人： Yi Su ,  Anup Bhalla ,  Daniel Ng

    IPC分类号： H01L21/822

    CPC分类号： H01L29/7813 ,  H01L27/0255 ,  H01L27/0629 ,  H01L29/0615 ,  H01L29/0638 ,  H01L29/0646 ,  H01L29/0692 ,  H01L29/0696 ,  H01L29/66734 ,  H01L29/7803 ,  H01L29/7804 ,  H01L29/7808 ,  H01L29/7811 ,  H01L29/7815 ,  H01L29/8611 ,  H01L29/866 ,  H01L2924/0002 ,  H01L2924/00

    摘要： A semiconductor power device supported on a semiconductor substrate comprising a plurality of transistor cells each having a source and a drain with a gate to control an electric current transmitted between the source and the drain. The semiconductor further includes a gate-to-drain (GD) clamp termination connected in series between the gate and the drain further includes a plurality of back-to-back polysilicon diodes connected in series to a silicon diode includes parallel doped columns in the semiconductor substrate wherein the parallel doped columns having a predefined gap. The doped columns further include a U-shaped bend column connect together the ends of parallel doped columns with a deep doped well disposed below and engulfing the U-shaped bend.

    摘要翻译： 一种半导体功率器件，其被支撑在半导体衬底上，该半导体衬底包括多个晶体管单元，每个晶体管单元具有源极和漏极，栅极用于控制在源极和漏极之间传输的电流。 半导体还包括在栅极和漏极之间串联连接的栅极 - 漏极（GD）钳位端接器，还包括串联连接到硅二极管的多个背对背多晶硅二极管，包括半导体中的并行掺杂的列 衬底，其中平行掺杂的柱具有预定的间隙。 掺杂的柱还包括U形弯曲柱，其将平行掺杂的柱的端部连接在一起，深度掺杂的阱设置在U形弯曲部下方并吞噬U形弯曲部。

    INTEGRATION OF A SENSE FET INTO A DISCRETE POWER MOSFET
    103.
    发明申请
    INTEGRATION OF A SENSE FET INTO A DISCRETE POWER MOSFET 有权
    将感测FET集成到分立功率MOSFET中

    公开(公告)号：US20100314693A1

    公开(公告)日：2010-12-16

    申请号：US12860777

    申请日：2010-08-20

    申请人： YI SU ,  Anup Bhalla ,  Daniel Ng

    发明人： YI SU ,  Anup Bhalla ,  Daniel Ng

    IPC分类号： H01L27/088

    CPC分类号： H01L29/7813 ,  H01L21/8234 ,  H01L27/088 ,  H01L29/0646 ,  H01L29/0653 ,  H01L29/0696 ,  H01L29/66734 ,  H01L29/7815 ,  H01L2224/0603 ,  H01L2924/13091 ,  H01L2924/00

    摘要： A semiconductor device includes a main field effect transistor (FET) and one or more sense FETs, and a common gate pad. The main FET and the one or more sense FETs are formed in a common substrate. The main FET and each of the sense FETs include a source terminal, a gate terminal and a drain terminal. The common gate pad connects the gate terminals of the main FET and the one or more sense FETs. An electrical isolation is disposed between the gate terminals of the main FET and the one or more sense FETs. Embodiments of this invention may be applied to both N-channel and P-channel MOSFET devices.

    摘要翻译： 半导体器件包括主场效应晶体管（FET）和一个或多个感测FET以及公共栅极焊盘。 主FET和一个或多个感测FET形成在公共衬底中。 主FET和每个感测FET包括源极端子，栅极端子和漏极端子。 公共栅极焊盘连接主FET和一个或多个感测FET的栅极端子。 在主FET和一个或多个感测FET的栅极端子之间设置电隔离。 本发明的实施例可以应用于N沟道和P沟道MOSFET器件。

    Power mosfet device structure for high frequency applications
    104.
    发明申请
    Power mosfet device structure for high frequency applications 有权
    用于高频应用的电源mosfet器件结构

    公开(公告)号：US20100148246A1

    公开(公告)日：2010-06-17

    申请号：US12658450

    申请日：2010-02-09

    申请人： Anup Bhalla ,  Daniel Ng ,  Tiesheng Li ,  Sik K. Lui

    发明人： Anup Bhalla ,  Daniel Ng ,  Tiesheng Li ,  Sik K. Lui

    IPC分类号： H01L29/78 ,  H01L21/336

    CPC分类号： H01L29/66712 ,  H01L29/0878 ,  H01L29/1095 ,  H01L29/402 ,  H01L29/41741 ,  H01L29/41775 ,  H01L29/42368 ,  H01L29/42372 ,  H01L29/42376 ,  H01L29/66719 ,  H01L29/66727 ,  H01L29/7802 ,  H01L29/7811 ,  H01L29/7827

    摘要： This invention discloses a new switching device supported on a semiconductor that includes a drain disposed on a first surface and a source region disposed near a second surface of said semiconductor opposite the first surface. The switching device further includes an insulated gate electrode disposed on top of the second surface for controlling a source to drain current. The switching device further includes a source electrode interposed into the insulated gate electrode for substantially preventing a coupling of an electrical field between the gate electrode and an epitaxial region underneath the insulated gate electrode. The source electrode further covers and extends over the insulated gate for covering an area on the second surface of the semiconductor to contact the source region. The semiconductor substrate further includes an epitaxial layer disposed above and having a different dopant concentration than the drain region. The insulated gate electrode further includes an insulation layer for insulating the gate electrode from the source electrode wherein the insulation layer having a thickness depending on a Vgsmax rating of the vertical power device.

    摘要翻译： 本发明公开了一种支撑在半导体上的新开关装置，其包括设置在第一表面上的漏极和设置在与第一表面相对的所述半导体的第二表面附近的源极区域。 开关装置还包括设置在第二表面顶部的用于控制源极到漏极电流的绝缘栅电极。 开关装置还包括插入到绝缘栅电极中的源电极，用于基本上防止栅电极和绝缘栅电极下方的外延区之间的电场的耦合。 源电极进一步覆盖并延伸在绝缘栅上，以覆盖半导体的第二表面上的区域以接触源区。 半导体衬底还包括设置在漏极区以上且具有与漏极区不同的掺杂浓度的外延层。 绝缘栅电极还包括用于使栅电极与源电极绝缘的绝缘层，其中绝缘层的厚度取决于垂直功率器件的Vgsmax等级。

    Calibration technique for measuring gate resistance of power MOS gate device at wafer level
    105.
    发明申请
    Calibration technique for measuring gate resistance of power MOS gate device at wafer level 有权
    用于在晶圆级测量功率MOS栅极器件的栅极电阻的校准技术

    公开(公告)号：US20070096093A1

    公开(公告)日：2007-05-03

    申请号：US11265363

    申请日：2005-11-01

    申请人： Anup Bhalla ,  Sik-K. Lui ,  Daniel Ng

    发明人： Anup Bhalla ,  Sik-K. Lui ,  Daniel Ng

    IPC分类号： H01L23/58 ,  H01L21/66

    CPC分类号： H04L63/102 ,  G01R31/2625 ,  G01R31/2884 ,  G01R35/005 ,  H01L22/14 ,  H01L2924/0002 ,  H04L63/08 ,  H01L2924/00

    摘要： This invention discloses a method for calibrating a gate resistance measurement of a semiconductor power device that includes a step of forming a RC network on a test area on a semiconductor wafer adjacent to a plurality of semiconductor power chips and measuring a resistance and a capacitance of the RC network to prepare for carrying out a wafer-level measurement calibration of the semiconductor power device. The method further includes a step of connecting a probe card to a set of contact pads on the semiconductor wafer for carrying out the wafer-level measurement calibration followed by performing a gate resistance Rg measurement for the semiconductor power chips.

    摘要翻译： 本发明公开了一种用于校准半导体功率器件的栅极电阻测量的方法，包括在与多个半导体功率芯片相邻的半导体晶片上的测试区域上形成RC网络的步骤，并测量电阻和电容 RC网络，准备进行半导体功率器件的晶圆级测量校准。 该方法还包括将探针卡连接到半导体晶片上的一组接触焊盘，以执行晶片级测量校准，然后对半导体功率芯片执行栅极电阻Rg测量。

    Cobalt silicon contact barrier metal process for high density semiconductor power devices
    106.
    发明申请
    Cobalt silicon contact barrier metal process for high density semiconductor power devices 审中-公开
    用于高密度半导体功率器件的钴硅接触屏障金属工艺

    公开(公告)号：US20070075360A1

    公开(公告)日：2007-04-05

    申请号：US11240255

    申请日：2005-09-30

    申请人： Hong Chang ,  Tiesheng Li ,  Sung-Shan Tai ,  Daniel Ng ,  Anup Bhalla

    发明人： Hong Chang ,  Tiesheng Li ,  Sung-Shan Tai ,  Daniel Ng ,  Anup Bhalla

    IPC分类号： H01L29/78 ,  H01L21/336

    CPC分类号： H01L29/7813 ,  H01L21/28518 ,  H01L21/76843 ,  H01L21/76855 ,  H01L29/456 ,  H01L29/4933 ,  H01L29/4941 ,  H01L29/66734 ,  H01L29/7811

    摘要： This invention discloses an improved trenched metal oxide semiconductor field effect transistor (MOSFET) cell that includes a trenched gate surrounded by a source region encompassed in a body region above a drain region disposed on a bottom surface of a substrate. The MOSFET cell further includes a source contact opening opened on top of an area extended over the body region and the source region through a protective insulation layer wherein the area further has a cobalt-silicide layer disposed near a top surface of the substrate. The MOSFET cell further includes a Ti/TiN conductive layer covering the area interfacing with the cobalt-silicide layer over the source contact opening. The MOSFET cell further includes a source contact metal layer formed on top of the Ti/TiN conductive layer ready to form source-bonding wires thereon.

    摘要翻译： 本发明公开了一种改进的沟槽金属氧化物半导体场效应晶体管（MOSFET）单元，其包括被包围在设置在基板的底表面上的漏极区域上方的体区域中的源极区域包围的沟槽栅极。 MOSFET单元进一步包括源极接触开口，该开口位于通过保护绝缘层延伸到主体区域上的区域的顶部，并且源区域通过保护绝缘层开放，其中该区域还具有设置在基板顶表面附近的硅化钴层。 MOSFET单元还包括覆盖源极接触开口上与硅化钴层接合的区域的Ti / TiN导电层。 MOSFET单元还包括形成在Ti / TiN导电层的顶部上的源极接触金属层，准备在其上形成源极接合线。

    Power MOSFET device structure for high frequency applications
    107.
    发明申请
    Power MOSFET device structure for high frequency applications 有权
    功率MOSFET器件结构用于高频应用

    公开(公告)号：US20060249785A1

    公开(公告)日：2006-11-09

    申请号：US11125506

    申请日：2005-05-09

    申请人： Anup Bhalla ,  Daniel Ng ,  Tiesheng Li ,  Sik Lui

    发明人： Anup Bhalla ,  Daniel Ng ,  Tiesheng Li ,  Sik Lui

    IPC分类号： H01L29/78 ,  H01L21/336

    CPC分类号： H01L29/66712 ,  H01L29/0878 ,  H01L29/1095 ,  H01L29/402 ,  H01L29/41741 ,  H01L29/41775 ,  H01L29/42368 ,  H01L29/42372 ,  H01L29/42376 ,  H01L29/66719 ,  H01L29/66727 ,  H01L29/7802 ,  H01L29/7811 ,  H01L29/7827

    摘要： This invention discloses a new switching device supported on a semiconductor that includes a drain disposed on a first surface and a source region disposed near a second surface of said semiconductor opposite the first surface. The switching device further includes an insulated gate electrode disposed on top of the second surface for controlling a source to drain current. The switching device further includes a source electrode interposed into the insulated gate electrode for substantially preventing a coupling of an electrical field between the gate electrode and an epitaxial region underneath the insulated gate electrode. The source electrode further covers and extends over the insulated gate for covering an area on the second surface of the semiconductor to contact the source region. The semiconductor substrate further includes an epitaxial layer disposed above and having a different dopant concentration than the drain region. The insulated gate electrode further includes an insulation layer for insulating the gate electrode from the source electrode wherein the insulation layer having a thickness depending on a Vgsmax rating of the vertical power device.

    摘要翻译： 本发明公开了一种支撑在半导体上的新开关装置，其包括设置在第一表面上的漏极和设置在与第一表面相对的所述半导体的第二表面附近的源极区域。 开关装置还包括设置在第二表面顶部的用于控制源极到漏极电流的绝缘栅电极。 开关装置还包括插入到绝缘栅电极中的源电极，用于基本上防止栅电极和绝缘栅电极下方的外延区之间的电场的耦合。 源电极进一步覆盖并延伸在绝缘栅上，以覆盖半导体的第二表面上的区域以接触源区。 半导体衬底还包括设置在漏极区以上且具有与漏极区不同的掺杂浓度的外延层。 绝缘栅电极还包括用于使栅电极与源电极绝缘的绝缘层，其中绝缘层的厚度取决于垂直功率器件的Vgsmax等级。

    Self-aligned slotted accumulation-mode field effect transistor (ACCUFET) structure and method
    108.
    发明授权
    Self-aligned slotted accumulation-mode field effect transistor (ACCUFET) structure and method 有权

    公开(公告)号：US10468526B2

    公开(公告)日：2019-11-05

    申请号：US15836756

    申请日：2017-12-08

    申请人： François Hébert ,  Madhur Bobde ,  Anup Bhalla

    发明人： François Hébert ,  Madhur Bobde ,  Anup Bhalla

    IPC分类号： H01L29/78 ,  H01L29/66 ,  H01L29/06 ,  H01L21/265 ,  H01L29/417 ,  H01L29/45 ,  H01L29/47 ,  H01L29/08

    摘要： This invention discloses a semiconductor power device disposed in a semiconductor substrate. The semiconductor power device includes trenched gates each having a stick-up gate segment extended above a top surface of the semiconductor substrate surrounded by sidewall spacers. The semiconductor power device further includes slots opened aligned with the sidewall spacers substantially parallel to the trenched gates. The stick-up gate segment further includes a cap composed of an insulation material surrounded by the sidewall spacers. A layer of barrier metal covers a top surface of the cap and over the sidewall spacers and extends above a top surface of the slots. The slots are filled with a gate material same as the gate segment for functioning as additional gate electrodes for providing a depletion layer extends toward the trenched gates whereby a drift region between the slots and the trenched gate is fully depleted at a gate-to-drain voltage Vgs=0 volt.