公开(公告)号：US20160141393A1

公开(公告)日：2016-05-19

申请号：US15003370

申请日：2016-01-21

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Jan Hoentschel ,  Stefan Flachowsky ,  Andreas Kurz ,  Sven Beyer ,  Wolfgang Buchholtz

IPC: H01L29/66 ,  H01L21/308 ,  H01L49/02 ,  H01L21/02

CPC classification number: H01L29/66795 ,  H01L21/02164 ,  H01L21/308 ,  H01L21/823431 ,  H01L21/845 ,  H01L27/0629 ,  H01L27/0738 ,  H01L28/20 ,  H01L29/66545

Abstract: A method includes forming a plurality of fins in a semiconductor substrate using a common patterning process. A conductive layer is formed above the plurality of fins. A mask is formed above the conductive layer. The conductive layer is etched using the mask to define trenches in the conductive layer. A first insulating layer is formed above the conductive layer and in the trenches. First and second contacts are formed connected to respective ends of the conductive layer.

Abstract translation: 一种方法包括使用共同的图案化工艺在半导体衬底中形成多个翅片。 在多个翅片上方形成导电层。 在导电层上方形成掩模。 使用掩模蚀刻导电层以在导电层中限定沟槽。 第一绝缘层形成在导电层上方和沟槽中。 第一和第二触点形成为连接到导电层的相应末端。

公开(公告)号：US20160118499A1

公开(公告)日：2016-04-28

申请号：US14521939

申请日：2014-10-23

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Hans-Peter Moll ,  Peter Baars ,  Jan Hoentschel

IPC: H01L29/78 ,  H01L29/66 ,  H01L29/06

CPC classification number: H01L29/7848 ,  H01L21/76224 ,  H01L21/823878 ,  H01L29/0649 ,  H01L29/0653 ,  H01L29/0847 ,  H01L29/1054 ,  H01L29/161 ,  H01L29/165 ,  H01L29/66568 ,  H01L29/66628 ,  H01L29/66772 ,  H01L29/7838 ,  H01L29/7849 ,  H01L29/78603 ,  H01L29/78639 ,  H01L29/78654

Abstract: The present disclosure provides in some aspects a semiconductor device and a method of forming a semiconductor device. According to some illustrative embodiments herein, the semiconductor device includes an active region formed in a semiconductor substrate, a gate structure disposed over the active region, source/drain regions formed in the active region in alignment with the gate structure, and an insulating material region buried into the active region under the gate structure, wherein the insulating material region is surrounded by the active region and borders a channel region in the active region below the gate structure along a depth direction of the active region.

Abstract translation: 本公开在一些方面提供半导体器件和形成半导体器件的方法。 根据这里的一些说明性实施例，半导体器件包括形成在半导体衬底中的有源区，设置在有源区上的栅极结构，形成在与栅极结构对准的有源区中的源/漏区，以及绝缘材料区 埋入栅极结构下的有源区，其中绝缘材料区域被有源区域包围，并且沿着有源区域的深度方向与栅极结构下方的有源区域中的沟道区域相邻。

公开(公告)号：US20150372100A1

公开(公告)日：2015-12-24

申请号：US14309586

申请日：2014-06-19

Applicant: GLOBALFOUNDRIES, Inc.

Inventor： Gerd Zschätzsch ,  Stefan Flachowsky ,  Jan Hoentschel

IPC: H01L29/40 ,  H01L29/78 ,  H01L29/417

CPC classification number: H01L29/7848 ,  H01L21/28518 ,  H01L21/28525 ,  H01L21/76843 ,  H01L21/76855 ,  H01L21/76879 ,  H01L21/823814 ,  H01L21/823871 ,  H01L23/485 ,  H01L29/165 ,  H01L29/41725 ,  H01L29/665 ,  H01L29/66628 ,  H01L29/66636 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Integrated circuits having improved contacts and improved methods for fabricating integrated circuits having contacts are provided. In an embodiment, a method for fabricating an integrated circuit includes providing a semiconductor substrate with a source/drain region. The method deposits an interlayer dielectric material over the semiconductor substrate. Further, the method etches the interlayer dielectric material to form a hole defining an exposed portion of the source/drain region. The method includes forming a contact forming a contact in the hole over the exposed portion of the source/drain region and forming an interconnect in the hole over the contact.

Abstract translation: 提供具有改进的接触的集成电路和用于制造具有触点的集成电路的改进方法。 在一个实施例中，一种用于制造集成电路的方法包括：提供具有源极/漏极区域的半导体衬底。 该方法在半导体衬底上沉积层间电介质材料。 此外，该方法蚀刻层间电介质材料以形成限定源极/漏极区域的暴露部分的孔。 该方法包括在源极/漏极区域的暴露部分上形成在孔中形成接触的接触，并且在接触件上方的孔中形成互连。

公开(公告)号：US09190516B2

公开(公告)日：2015-11-17

申请号：US14186387

申请日：2014-02-21

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Ran Yan ,  Stefan Flachowsky ,  Alban Zaka ,  Jan Hoentschel

IPC: H01L29/78 ,  H01L29/161 ,  H01L29/08 ,  H01L29/66 ,  H01L21/02 ,  H01L21/265 ,  H01L21/3065 ,  H01L29/167 ,  H01L29/417 ,  H01L21/8234

CPC classification number: H01L29/7848 ,  H01L21/0245 ,  H01L21/02532 ,  H01L21/02639 ,  H01L21/26506 ,  H01L21/26513 ,  H01L21/26586 ,  H01L21/3065 ,  H01L21/823412 ,  H01L21/823418 ,  H01L21/823425 ,  H01L29/045 ,  H01L29/0843 ,  H01L29/0847 ,  H01L29/161 ,  H01L29/165 ,  H01L29/167 ,  H01L29/41725 ,  H01L29/66477 ,  H01L29/66636

Abstract: A methodology for forming a compressive strain layer with increased thickness that exhibits improved device performance and the resulting device are disclosed. Embodiments may include forming a recess in a source or drain region of a substrate, implanting a high-dose impurity in a surface of the recess, and depositing a silicon-germanium (SiGe) layer in the recess.

Abstract translation: 公开了一种用于形成具有提高的器件性能的具有增加的厚度的压缩应变层的方法以及所得到的器件。 实施例可以包括在衬底的源极或漏极区域中形成凹陷，在凹部的表面中注入高剂量杂质，以及在凹部中沉积硅 - 锗（SiGe）层。

公开(公告)号：US09165840B2

公开(公告)日：2015-10-20

申请号：US14579255

申请日：2014-12-22

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Stefan Flachowsky ,  Matthias Kessler ,  Jan Hoentschel

IPC: H01L21/00 ,  H01L21/84 ,  H01L21/02 ,  H01L21/8238 ,  H01L21/762 ,  H01L29/66 ,  H01L27/12 ,  H01L27/06 ,  H01L21/8234 ,  H01L29/94 ,  H01L27/088

CPC classification number: H01L21/84 ,  H01L21/02428 ,  H01L21/76283 ,  H01L21/823412 ,  H01L21/823878 ,  H01L27/0629 ,  H01L27/088 ,  H01L27/1207 ,  H01L29/0649 ,  H01L29/16 ,  H01L29/20 ,  H01L29/66181 ,  H01L29/7786 ,  H01L29/78 ,  H01L29/861 ,  H01L29/945

Abstract: A structure comprises a semiconductor substrate, a semiconductor-on-insulator region and a bulk region. The semiconductor-on-insulator region comprises a first semiconductor region, a dielectric layer provided between the semiconductor substrate and the first semiconductor region, and a first transistor comprising an active region provided in the first semiconductor region. The dielectric layer provides electrical isolation between the first semiconductor region and the semiconductor substrate. The bulk region comprises a second semiconductor region provided directly on the semiconductor substrate.

Abstract translation: 一种结构包括半导体衬底，绝缘体上半导体区域和体区域。 绝缘体上半导体区域包括第一半导体区域，设置在半导体衬底和第一半导体区域之间的电介质层，以及包括设置在第一半导体区域中的有源区的第一晶体管。 电介质层在第一半导体区域和半导体衬底之间提供电隔离。 本体区域包括直接设置在半导体衬底上的第二半导体区域。

公开(公告)号：US09087716B2

公开(公告)日：2015-07-21

申请号：US13942034

申请日：2013-07-15

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Ran Yan ,  Joerg Schoenekess ,  Jan Hoentschel

IPC: H01L21/8238 ,  H01L27/088 ,  H01L29/66 ,  H01L21/8234 ,  H01L21/84 ,  H01L27/092

CPC classification number: H01L27/088 ,  H01L21/823412 ,  H01L21/823807 ,  H01L21/84 ,  H01L27/092 ,  H01L29/66477

Abstract: The present disclosure provides an improved method for forming a thin semiconductor alloy layer on top of a semiconductor layer. The proposed method relies on an implantation of appropriate impurity species before performing deposition of the semiconductor alloy film. The implanted species cause the semiconductor alloy layer to be less unstable to wet and dry etches performed on the device surface after deposition. Thus, the thickness uniformity of the semiconductor alloy film may be substantially increased if the film is deposited after performing the implantation. On the other hand, some implanted impurities have been found to decrease the growth rate of the semiconductor alloy layer. Thus, by selectively implanting appropriate impurities in predetermined portions of a wafer, a single deposition step may be used in order to form a semiconductor alloy layer with a thickness which may be locally adjusted at will.

Abstract translation: 本公开提供了一种用于在半导体层的顶部上形成薄半导体合金层的改进方法。 所提出的方法依赖于在进行半导体合金膜的沉积之前植入适当的杂质物质。 植入的物质导致半导体合金层在沉积后在器件表面上进行的湿法干蚀刻不太稳定。 因此，如果在进行植入之后沉积膜，则半导体合金膜的厚度均匀性可以显着增加。 另一方面，已经发现一些植入的杂质降低了半导体合金层的生长速率。 因此，通过在晶片的预定部分中选择性地注入适当的杂质，可以使用单个沉积步骤以形成具有可以随意局部调整的厚度的半导体合金层。

公开(公告)号：US20150129966A1

公开(公告)日：2015-05-14

申请号：US14600097

申请日：2015-01-20

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Stefan Flachowsky ,  Jan Hoentschel

IPC: H01L29/417 ,  H01L29/10 ,  H01L29/06 ,  H01L29/78

CPC classification number: H01L29/41783 ,  H01L29/0649 ,  H01L29/1033 ,  H01L29/42392 ,  H01L29/66545 ,  H01L29/66742 ,  H01L29/66772 ,  H01L29/78 ,  H01L29/78603 ,  H01L29/78609 ,  H01L29/78696

Abstract: A semiconductor structure comprises a substrate and a transistor. The transistor comprises a raised source region and a raised drain region provided above the substrate, one or more elongated semiconductor lines, a gate electrode and a gate insulation layer. The one or more elongated semiconductor lines are connected between the raised source region and the raised drain region, wherein a longitudinal direction of each of the one or more elongated semiconductor lines extends substantially along a horizontal direction that is perpendicular to a thickness direction of the substrate. Each of the elongated semiconductor lines comprises a channel region. The gate electrode extends all around each of the channel regions of the one or more elongated semiconductor lines. The gate insulation layer is provided between each of the one or more elongated semiconductor lines and the gate electrode.

Abstract translation: 半导体结构包括衬底和晶体管。 晶体管包括设置在衬底上方的升高的源极区域和升高的漏极区域，一个或多个细长半导体管线，栅极电极和栅极绝缘层。 所述一个或多个细长半导体线连接在所述升高的源极区域和所述隆起的漏极区域之间，其中所述一个或多个细长半导体线路中的每一个的纵向方向基本上沿着垂直于所述衬底的厚度方向的水平方向延伸 。 每个细长半导体线包括沟道区。 栅电极围绕一个或多个细长半导体线路的每个沟道区域延伸。 栅极绝缘层设置在一个或多个细长半导体线路和栅电极中的每一个之间。

公开(公告)号：US20140264632A1

公开(公告)日：2014-09-18

申请号：US14167001

申请日：2014-01-29

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Ralf Richter ,  Jan Hoentschel ,  Peter Javorka

IPC: H01L29/78 ,  H01L29/66

CPC classification number: H01L29/66795 ,  H01L29/41791 ,  H01L29/7833 ,  H01L29/7845 ,  H01L29/785

Abstract: A semiconductor structure is provided including a transistor, the transistor including one or more elongated semiconductor regions, each of the one or more elongated semiconductor regions having a channel region, a gate electrode, wherein the gate electrode is provided at least at two opposite sides of each of the one or more elongated semiconductor regions, and a layer of a stress-creating material, the stress-creating material providing a variable stress, wherein the layer of stress-creating material is arranged to provide a stress at least in the channel region of each of the one or more elongated semiconductor regions, the stress provided in the channel region of each of the one or more elongated semiconductor regions being variable.

Abstract translation: 提供了包括晶体管的半导体结构，所述晶体管包括一个或多个细长半导体区域，所述一个或多个细长半导体区域中的每一个具有沟道区域，栅极电极，其中所述栅电极至少设置在 所述一个或多个细长半导体区域中的每一个以及应力产生材料层，所述应力产生材料提供可变应力，其中所述应力产生材料层被布置成至少在所述沟道区域中提供应力 所述一个或多个细长半导体区域中的每个的沟道区域中提供的应力是可变的。

公开(公告)号：US20140264617A1

公开(公告)日：2014-09-18

申请号：US14175288

申请日：2014-02-07

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Peter Javorka ,  Juergen Faul ,  Ralf Richter ,  Jan Hoentschel

IPC: H01L27/088 ,  H01L21/28

CPC classification number: H01L27/0883 ,  H01L21/26586 ,  H01L21/28 ,  H01L21/28255 ,  H01L21/823412 ,  H01L21/823807 ,  H01L29/1041 ,  H01L29/1054 ,  H01L29/1083 ,  H01L29/495 ,  H01L29/51 ,  H01L29/66537 ,  H01L29/6659 ,  H01L29/66651

Abstract: The present disclosure provides semiconductor device structures with a first PMOS active region and a second PMOS active region provided within a semiconductor substrate. A silicon germanium channel layer is only formed over the second PMOS active region. Gate electrodes are formed over the first and second PMOS active regions, wherein the gate electrode over the second PMOS active region is formed over the silicon germanium channel.

Abstract translation: 本公开提供半导体器件结构，其具有设置在半导体衬底内的第一PMOS有源区和第二PMOS有源区。 硅锗沟道层仅形成在第二PMOS有源区上。 栅电极形成在第一和第二PMOS有源区上，其中第二PMOS有源区上的栅电极形成在硅锗通道上。

公开(公告)号：US20140264386A1

公开(公告)日：2014-09-18

申请号：US14287806

申请日：2014-05-27

Applicant: GLOBALFOUNDRIES Inc,

Inventor： Jan Hoentschel ,  Vassilios Papageorgiou ,  Belinda Hannon

IPC: H01L27/092 ,  H01L29/78 ,  H01L29/16

CPC classification number: H01L27/092 ,  H01L21/26506 ,  H01L21/26513 ,  H01L21/26586 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/84 ,  H01L27/1203 ,  H01L29/1033 ,  H01L29/1083 ,  H01L29/1608 ,  H01L29/165 ,  H01L29/665 ,  H01L29/6653 ,  H01L29/6656 ,  H01L29/66636 ,  H01L29/7833 ,  H01L29/7843 ,  H01L29/7847 ,  H01L29/7848

Abstract: A semiconductor device includes a first transistor having first drain and source regions and a first channel region and a second transistor having second drain and source regions and a second channel region. A first silicon/carbon alloy material is embedded in the first drain and source regions, the first silicon/carbon alloy material inducing a first strain component along a first channel length direction of the first channel region. A second silicon/carbon alloy material is embedded in the second drain and source regions, the second silicon/carbon alloy material inducing a second strain component along a second channel length direction of the second channel region, wherein the second strain component is of an opposite type of the first strain component.

Abstract translation: 半导体器件包括具有第一漏极和源极区域的第一晶体管和第一沟道区域以及具有第二漏极和源极区域以及第二沟道区域的第二晶体管。 第一硅/碳合金材料嵌入在第一漏极和源极区域中，第一硅/碳合金材料沿着第一沟道区域的第一沟道长度方向诱导第一应变分量。 第二硅/碳合金材料嵌入在第二漏极和源极区域中，第二硅/碳合金材料沿着第二沟道区域的第二沟道长度方向诱导第二应变分量，其中第二应变分量是相反的 类型的第一应变分量。