公开(公告)号：US08701273B2

公开(公告)日：2014-04-22

申请号：US13456932

申请日：2012-04-26

申请人： Yoshitaka Sasaki ,  Hiroyuki Ito ,  Hironori Araki ,  Seiichiro Tomita ,  Kazuki Sato ,  Shigeki Tanemura ,  Tatsuya Shimizu

发明人： Yoshitaka Sasaki ,  Hiroyuki Ito ,  Hironori Araki ,  Seiichiro Tomita ,  Kazuki Sato ,  Shigeki Tanemura ,  Tatsuya Shimizu

IPC分类号： G11B5/127 ,  H04R31/00 ,  G11B5/265 ,  G11B5/31 ,  G11B5/17

CPC分类号： G11B5/1278 ,  G11B5/1276 ,  G11B5/17 ,  G11B5/265 ,  G11B5/2651 ,  G11B5/2658 ,  G11B5/3116 ,  G11B5/3123 ,  G11B5/315 ,  G11B5/3153 ,  G11B5/3163 ,  Y10T29/49032 ,  Y10T29/49043 ,  Y10T29/49044 ,  Y10T29/49046 ,  Y10T29/49048 ,  Y10T29/49052

摘要： A method of manufacturing a magnetic head includes the step of forming an accommodation part and the step of forming a return path section. The return path section lies between a main pole and a top surface of a substrate, and connects a shield and part of the main pole away from a medium facing surface to each other so that a space through which part of a coil passes is defined. The accommodation part accommodates at least part of the return path section. The step of forming the return path section forms first to third portions simultaneously. The first portion is located closer to the top surface of the substrate than is the space. The second portion is located closer to the medium facing surface than is the space. The third portion is located farther from the medium facing surface than is the space.

摘要翻译： 制造磁头的方法包括形成容纳部的步骤和形成返回路径部的步骤。 返回路径部分位于基板的主极和顶表面之间，并且将屏蔽和主极的一部分远离介质相对表面彼此连接，从而限定线圈通过的空间。 容纳部分容纳返回路径部分的至少一部分。 形成返回路径部分的步骤同时形成第一至第三部分。 第一部分位于比空间更靠近衬底顶表面的位置。 第二部分比空间更靠近介质面向表面。 第三部分位于比介质相对表面更远离空间。

公开(公告)号：US20140080259A1

公开(公告)日：2014-03-20

申请号：US13621540

申请日：2012-09-17

申请人： Yoshitaka Sasaki ,  Hiroyuki Ito ,  Atsushi Iijima ,  Ryuji Fujii

发明人： Yoshitaka Sasaki ,  Hiroyuki Ito ,  Atsushi Iijima ,  Ryuji Fujii

IPC分类号： H01L21/82

CPC分类号： H01L24/96 ,  H01L21/6835 ,  H01L22/22 ,  H01L24/24 ,  H01L24/94 ,  H01L25/0657 ,  H01L25/105 ,  H01L25/50 ,  H01L2221/68327 ,  H01L2221/6834 ,  H01L2224/24145 ,  H01L2224/32145 ,  H01L2224/83005 ,  H01L2224/94 ,  H01L2225/06524 ,  H01L2225/06527 ,  H01L2225/06551 ,  H01L2225/06565 ,  H01L2225/1035 ,  H01L2225/1058 ,  H01L2224/03 ,  H01L2224/83

摘要： In a manufacturing method for layered chip packages, a layered substructure with at least one additional package joined thereto is used to produce a plurality of layered chip packages. The layered substructure includes a plurality of main bodies to be separated from each other later. Each main body includes: a main part having top and bottom surfaces and including a plurality of layer portions stacked on each other; and a plurality of main terminals disposed on at least one of the top and bottom surfaces of the main part. The additional package includes an additional semiconductor chip and at least one additional terminal that is electrically connected to the additional semiconductor chip and in contact with at least one of the plurality of main terminals.

摘要翻译： 在层叠芯片封装的制造方法中，使用具有与其连接的至少一个附加封装的分层子结构来制造多个分层芯片封装。 分层子结构包括稍后要彼此分离的多个主体。 每个主体包括：具有顶表面和底表面并且包括彼此堆叠的多个层部分的主要部分; 以及设置在主要部件的顶表面和底表面中的至少一个上的多个主端子。 附加封装包括附加的半导体芯片和至少一个额外的端子，其电连接到附加的半导体芯片并与多个主端子中的至少一个接触。

公开(公告)号：US08669492B2

公开(公告)日：2014-03-11

申请号：US11825837

申请日：2007-07-09

申请人： Hiroyuki Ito ,  Tsutomu Kamizono ,  Shoichi Yamanaka

发明人： Hiroyuki Ito ,  Tsutomu Kamizono ,  Shoichi Yamanaka

IPC分类号： B60L1/02 ,  H05B1/00 ,  H05B3/00 ,  H05B11/00 ,  H05B1/02

CPC分类号： B60N2/5685 ,  B60N2/002

摘要： A passenger seat device includes a seat heater embedded in a seat and a detector electrode embedded underneath the seat heater. Electric power is supplied to the seat heater from an on-board battery through seat heater switches. Alternating voltage or current is supplied to the detector electrode. The detector electrode potential relative to the ground is lowered when the seat is occupied by a passenger. The changes in the potential of the detector electrode is detected by an occupant detector including a microcomputer. The detection is performed when the seat heater is brought to a floating state to suppress an amount of capacitance formed between the seat heater and the detector electrode. Thus, a sensitivity of the occupant detector is improved. The detector electrode may be eliminated, and the occupant conditions may be detected based on a potential of the seat heater to which alternating current or voltage is supplied.

摘要翻译： 乘客座椅装置包括嵌入在座椅中的座椅加热器和嵌入座椅加热器下方的检测器电极。 通过座椅加热器开关从车载电池向座椅加热器供电。 交流电压或电流被提供给检测器电极。 当座椅被乘客占用时，相对于地面的检测器电极电位降低。 检测器电极的电位变化由包括微型计算机的乘员检测器检测。 当座椅加热器处于浮动状态以抑制座椅加热器和检测器电极之间形成的电容量时，执行检测。 因此，乘员检测器的灵敏度提高。 可以消除检测器电极，并且可以基于供应有交流电或电压的座椅加热器的电位来检测乘员条件。

公开(公告)号：US08653639B2

公开(公告)日：2014-02-18

申请号：US13156808

申请日：2011-06-09

申请人： Yoshitaka Sasaki ,  Hiroyuki Ito ,  Hiroshi Ikejima ,  Atsushi Iijima

发明人： Yoshitaka Sasaki ,  Hiroyuki Ito ,  Hiroshi Ikejima ,  Atsushi Iijima

IPC分类号： H01L21/02

CPC分类号： H01L21/561 ,  H01L21/6835 ,  H01L22/22 ,  H01L23/3114 ,  H01L23/5389 ,  H01L24/03 ,  H01L24/05 ,  H01L24/11 ,  H01L24/13 ,  H01L24/16 ,  H01L24/24 ,  H01L24/25 ,  H01L24/27 ,  H01L24/29 ,  H01L24/32 ,  H01L24/75 ,  H01L24/81 ,  H01L24/82 ,  H01L24/83 ,  H01L24/92 ,  H01L24/94 ,  H01L24/95 ,  H01L25/0657 ,  H01L25/105 ,  H01L25/50 ,  H01L2221/68327 ,  H01L2221/6834 ,  H01L2224/02311 ,  H01L2224/02313 ,  H01L2224/02321 ,  H01L2224/0235 ,  H01L2224/02371 ,  H01L2224/02373 ,  H01L2224/02379 ,  H01L2224/0239 ,  H01L2224/024 ,  H01L2224/0345 ,  H01L2224/0346 ,  H01L2224/0401 ,  H01L2224/04026 ,  H01L2224/05008 ,  H01L2224/05013 ,  H01L2224/05147 ,  H01L2224/05644 ,  H01L2224/1146 ,  H01L2224/13024 ,  H01L2224/13144 ,  H01L2224/16148 ,  H01L2224/24011 ,  H01L2224/2405 ,  H01L2224/24146 ,  H01L2224/245 ,  H01L2224/2512 ,  H01L2224/25171 ,  H01L2224/25175 ,  H01L2224/25177 ,  H01L2224/2746 ,  H01L2224/29024 ,  H01L2224/29144 ,  H01L2224/32145 ,  H01L2224/32148 ,  H01L2224/75101 ,  H01L2224/8112 ,  H01L2224/81191 ,  H01L2224/81203 ,  H01L2224/81815 ,  H01L2224/82101 ,  H01L2224/82106 ,  H01L2224/83005 ,  H01L2224/8313 ,  H01L2224/83191 ,  H01L2224/83203 ,  H01L2224/83815 ,  H01L2224/8385 ,  H01L2224/83986 ,  H01L2224/92 ,  H01L2224/92244 ,  H01L2224/94 ,  H01L2224/95 ,  H01L2225/06541 ,  H01L2225/06551 ,  H01L2225/06558 ,  H01L2225/06565 ,  H01L2225/06593 ,  H01L2225/1058 ,  H01L2924/07802 ,  H01L2924/3511 ,  H01L2924/0105 ,  H01L2924/00014 ,  H01L2224/83 ,  H01L2224/11 ,  H01L2224/27 ,  H01L2224/82 ,  H01L2224/0231 ,  H01L21/78 ,  H01L2224/81 ,  H01L2924/00

摘要： A layered chip package includes a main body and wiring. The main body has a main part. The main part has a top surface and a bottom surface and includes a plurality of layer portions that are stacked. The wiring includes a plurality of lines passing through all the plurality of layer portions. Each layer portion includes a semiconductor chip and a plurality of electrodes. The semiconductor chip has a first surface, and a second surface opposite thereto. The plurality of electrodes are disposed on a side of the first surface of the semiconductor chip. The plurality of layer portions include two or more pairs of first and second layer portions in each of which the first and second layer portions are arranged so that the first or second surfaces of the respective semiconductor chips face each other. The plurality of electrodes include a plurality of first connection parts and a plurality of second connection parts. In the first layer portion, the plurality of first connection parts are in contact with the plurality of lines. In the second layer portion, the plurality of second connection parts are in contact with the plurality of lines.

摘要翻译： 分层芯片封装包括主体和布线。 主体有一个主要部分。 主要部分具有顶表面和底表面，并且包括堆叠的多个层部分。 布线包括穿过所有多个层部分的多条线。 各层部分包括半导体芯片和多个电极。 半导体芯片具有第一表面和与其相对的第二表面。 多个电极设置在半导体芯片的第一表面的一侧。 多个层部分包括两对或更多对第一和第二层部分，其中每个第一和第二层部分中的第一和第二层部分被布置成使得各个半导体芯片的第一或第二表面彼此面对。 多个电极包括多个第一连接部和多个第二连接部。 在第一层部分中，多个第一连接部分与多条线接触。 在第二层部分中，多个第二连接部分与多条线接触。

公开(公告)号：US08619517B1

公开(公告)日：2013-12-31

申请号：US13584185

申请日：2012-08-13

申请人： Yoshitaka Sasaki ,  Hiroyuki Ito ,  Shigeki Tanemura ,  Kazuki Sato ,  Hironori Araki

发明人： Yoshitaka Sasaki ,  Hiroyuki Ito ,  Shigeki Tanemura ,  Kazuki Sato ,  Hironori Araki

IPC分类号： G11B11/00

CPC分类号： G11B5/6088 ,  B82Y20/00 ,  G02B6/1226 ,  G11B5/3116 ,  G11B5/314 ,  G11B5/3163 ,  G11B2005/0021

摘要： A thermally-assisted magnetic recording head includes a waveguide having a core and a cladding, and a plasmon generator. The core has an evanescent light generating surface. The plasmon generator has a plasmon exciting part opposed to the evanescent light generating surface. Assuming a virtual straight line that passes internally through the core and that is parallel to the direction of travel of light propagating through the core, at least part of the evanescent light generating surface and at least part of the plasmon exciting part are both inclined relative to the virtual straight line such that the distance from the virtual straight line decreases with increasing proximity to the medium facing surface.

摘要翻译： 热辅助磁记录头包括具有芯和包层的波导和等离子体发生器。 核心具有ev逝的光生成面。 等离子体发生器具有与瞬逝光产生表面相对的等离子体激元部分。 假设虚拟直线在内部通过芯并且平行于传播通过芯的光的行进方向，至少部分渐逝光产生表面和至少部分等离子体激元部分都相对于 虚拟直线使得距离虚拟直线的距离随着与介质面对表面的接近程度的增加而减小。

公开(公告)号：US08618646B2

公开(公告)日：2013-12-31

申请号：US12902600

申请日：2010-10-12

申请人： Yoshitaka Sasaki ,  Hiroyuki Ito ,  Hiroshi Ikejima ,  Atsushi Iijima

发明人： Yoshitaka Sasaki ,  Hiroyuki Ito ,  Hiroshi Ikejima ,  Atsushi Iijima

IPC分类号： H01L23/02

CPC分类号： H01L24/92 ,  H01L22/22 ,  H01L24/03 ,  H01L24/05 ,  H01L24/13 ,  H01L24/16 ,  H01L24/96 ,  H01L25/0657 ,  H01L25/105 ,  H01L25/50 ,  H01L2224/03009 ,  H01L2224/0362 ,  H01L2224/037 ,  H01L2224/0401 ,  H01L2224/04105 ,  H01L2224/05008 ,  H01L2224/05011 ,  H01L2224/05012 ,  H01L2224/05147 ,  H01L2224/05569 ,  H01L2224/05644 ,  H01L2224/13144 ,  H01L2224/16145 ,  H01L2224/9202 ,  H01L2224/96 ,  H01L2225/06541 ,  H01L2225/06558 ,  H01L2225/06565 ,  H01L2225/1058 ,  H01L2924/00014 ,  H01L2924/07802 ,  H01L2924/1434 ,  H01L2924/181 ,  H01L2924/3511 ,  H01L2224/03 ,  H01L2924/0105 ,  H01L2924/00 ,  H01L2224/05552

摘要： A layered chip package includes a main body. The main body includes a main part, and further includes first terminals and second terminals disposed on the top and bottom surfaces of the main part, respectively. The main part includes first and second layer portions, and through electrodes penetrating them. The through electrodes are electrically connected to the first and second terminals. Each of the layer portions includes a semiconductor chip having a first surface and a second surface opposite thereto, and further includes surface electrodes. The surface electrodes are disposed on a side of the semiconductor chip opposite to the second surface. The first and second layer portions are bonded to each other such that the respective second surfaces face each other. The first terminals are formed by using the surface electrodes of the first layer portion. The second terminals are formed by using the surface electrodes of the second layer portion.

摘要翻译： 分层芯片封装包括主体。 主体包括主要部分，并且还包括分别设置在主要部分的顶表面和底表面上的第一端子和第二端子。 主要部分包括第一和第二层部分，以及贯穿它们的电极。 通孔电连接到第一和第二端子。 每个层部分包括具有第一表面和与其相对的第二表面的半导体芯片，并且还包括表面电极。 表面电极设置在与第二表面相对的半导体芯片的一侧上。 第一和第二层部分彼此接合，使得相应的第二表面彼此面对。 第一端子通过使用第一层部分的表面电极形成。 第二端子通过使用第二层部分的表面电极形成。

公开(公告)号：US08587125B2

公开(公告)日：2013-11-19

申请号：US12869471

申请日：2010-08-26

申请人： Yoshitaka Sasaki ,  Hiroyuki Ito ,  Atsushi Iijima

发明人： Yoshitaka Sasaki ,  Hiroyuki Ito ,  Atsushi Iijima

IPC分类号： H01L23/02 ,  H01L23/34 ,  H01L23/48 ,  H01L23/52 ,  H01L29/40 ,  H01L21/00

CPC分类号： H01L21/76898 ,  H01L21/563 ,  H01L21/6835 ,  H01L23/544 ,  H01L24/02 ,  H01L24/24 ,  H01L24/25 ,  H01L24/29 ,  H01L24/32 ,  H01L24/74 ,  H01L24/82 ,  H01L24/83 ,  H01L24/92 ,  H01L24/94 ,  H01L24/95 ,  H01L24/96 ,  H01L24/97 ,  H01L25/0657 ,  H01L25/50 ,  H01L2221/68327 ,  H01L2223/54406 ,  H01L2223/54433 ,  H01L2223/54453 ,  H01L2224/02311 ,  H01L2224/02313 ,  H01L2224/02321 ,  H01L2224/02371 ,  H01L2224/02375 ,  H01L2224/02379 ,  H01L2224/02381 ,  H01L2224/0239 ,  H01L2224/24011 ,  H01L2224/24145 ,  H01L2224/24146 ,  H01L2224/245 ,  H01L2224/2919 ,  H01L2224/32148 ,  H01L2224/82005 ,  H01L2224/821 ,  H01L2224/82101 ,  H01L2224/82106 ,  H01L2224/83005 ,  H01L2224/8385 ,  H01L2224/9202 ,  H01L2224/92244 ,  H01L2224/94 ,  H01L2224/95001 ,  H01L2224/96 ,  H01L2224/97 ,  H01L2225/06551 ,  H01L2225/06565 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/07802 ,  H01L2224/82 ,  H01L2924/00 ,  H01L2221/68304

摘要： A layered chip package includes a main body, and wiring including a plurality of wires disposed on a side surface of the main body. The main body includes a plurality of semiconductor chips stacked, and a plurality of electrodes that electrically connect the semiconductor chips to the wires. A method of manufacturing the layered chip package includes the steps of: fabricating a substructure that includes an array of a plurality of pre-separation main bodies and a plurality of holes for accommodating a plurality of preliminary wires, the holes being formed between two adjacent pre-separation main bodies; forming the preliminary wires in the plurality of holes by plating; and cutting the substructure so that the plurality of pre-separation main bodies are separated from each other and the preliminary wires are split into two sets of wires of two separate main bodies, whereby a plurality of layered chip packages are formed.

摘要翻译： 分层芯片封装包括主体和布置在主体的侧表面上的多根导线的布线。 主体包括堆叠的多个半导体芯片和将半导体芯片电连接到导线的多个电极。 制造层状芯片封装的方法包括以下步骤：制造包括多个预分离主体的阵列和用于容纳多条初级线的多个孔的子结构，所述孔形成在两个相邻的预制 分离主体; 通过电镀在多个孔中形成预备的电线; 并且切割所述子结构，使得所述多个预分离主体彼此分离，并且所述预备线被分成两组分离的主体的两组线，由此形成多个分层的芯片封装。

公开(公告)号：US08569878B2

公开(公告)日：2013-10-29

申请号：US12588659

申请日：2009-10-22

申请人： Yoshitaka Sasaki ,  Hiroyuki Ito ,  Atsushi Iijima

发明人： Yoshitaka Sasaki ,  Hiroyuki Ito ,  Atsushi Iijima

IPC分类号： H01L23/52 ,  H01L23/48 ,  H01L21/60

CPC分类号： H01L25/0652 ,  H01L21/56 ,  H01L23/3114 ,  H01L24/05 ,  H01L24/24 ,  H01L24/29 ,  H01L24/32 ,  H01L24/82 ,  H01L24/96 ,  H01L2221/68377 ,  H01L2224/02166 ,  H01L2224/0401 ,  H01L2224/05554 ,  H01L2224/13022 ,  H01L2224/16 ,  H01L2224/18 ,  H01L2224/73267 ,  H01L2225/06551 ,  H01L2924/01006 ,  H01L2924/01015 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01078 ,  H01L2924/01082 ,  H01L2924/07802 ,  H01L2924/14 ,  H01L2924/30105 ,  H01L2924/00

摘要： A semiconductor substrate has a plurality of groove portions formed along scribe lines. The semiconductor substrate includes: a device region in contact with at least any one of the plurality of groove portions and having a semiconductor device formed therein; a surface insulating layer formed to cover the device region and constituting a surface layer of the semiconductor substrate; and a wiring electrode connected to the semiconductor device and formed in a protruding shape rising above a surface of the surface insulating layer. The semiconductor substrate can be manufactured by forming a plurality of groove portions along scribe lines; applying an insulating material to a surface on a side where the plurality of groove portions are formed to form a surface insulating layer; and forming a wiring electrode connected to the semiconductor device and in a protruding shape rising above a surface of the surface insulating layer, after the formation of the surface insulating layer.

摘要翻译： 半导体基板具有沿划线形成的多个槽部。 半导体衬底包括：与多个沟槽部分中的至少一个接触并且具有形成在其中的半导体器件的器件区域; 形成为覆盖所述器件区域并构成所述半导体衬底的表面层的表面绝缘层; 以及连接到所述半导体器件并且形成为在所述表面绝缘层的表面上方上升的突出形状的布线电极。 可以通过沿划线形成多个槽部来制造半导体衬底; 将绝缘材料施加到形成所述多个槽部的一侧的表面上以形成表面绝缘层; 以及在形成所述表面绝缘层之后，形成连接到所述半导体器件并且以表面绝缘层的表面上方突出的形状的布线电极。

公开(公告)号：US08541887B2

公开(公告)日：2013-09-24

申请号：US12875710

申请日：2010-09-03

申请人： Yoshitaka Sasaki ,  Hiroyuki Ito ,  Hiroshi Ikejima ,  Atsushi Iijima

发明人： Yoshitaka Sasaki ,  Hiroyuki Ito ,  Hiroshi Ikejima ,  Atsushi Iijima

IPC分类号： H01L25/00

CPC分类号： H01L21/6835 ,  H01L21/563 ,  H01L23/3192 ,  H01L23/544 ,  H01L24/03 ,  H01L24/05 ,  H01L24/11 ,  H01L24/13 ,  H01L24/16 ,  H01L24/24 ,  H01L24/25 ,  H01L24/27 ,  H01L24/29 ,  H01L24/32 ,  H01L24/81 ,  H01L24/83 ,  H01L24/92 ,  H01L24/94 ,  H01L24/95 ,  H01L24/96 ,  H01L25/0657 ,  H01L25/105 ,  H01L25/16 ,  H01L25/50 ,  H01L2221/68327 ,  H01L2223/54406 ,  H01L2223/54433 ,  H01L2223/54453 ,  H01L2224/0231 ,  H01L2224/02311 ,  H01L2224/02313 ,  H01L2224/02321 ,  H01L2224/02371 ,  H01L2224/02375 ,  H01L2224/02379 ,  H01L2224/02381 ,  H01L2224/0239 ,  H01L2224/0345 ,  H01L2224/0346 ,  H01L2224/0401 ,  H01L2224/04026 ,  H01L2224/05008 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/1146 ,  H01L2224/13144 ,  H01L2224/16148 ,  H01L2224/24011 ,  H01L2224/24145 ,  H01L2224/24146 ,  H01L2224/245 ,  H01L2224/2746 ,  H01L2224/29144 ,  H01L2224/2919 ,  H01L2224/32148 ,  H01L2224/81121 ,  H01L2224/8113 ,  H01L2224/81191 ,  H01L2224/81193 ,  H01L2224/81203 ,  H01L2224/81815 ,  H01L2224/82005 ,  H01L2224/82101 ,  H01L2224/82106 ,  H01L2224/83005 ,  H01L2224/8313 ,  H01L2224/83191 ,  H01L2224/83193 ,  H01L2224/83203 ,  H01L2224/83444 ,  H01L2224/83815 ,  H01L2224/8385 ,  H01L2224/9202 ,  H01L2224/92244 ,  H01L2224/95001 ,  H01L2224/96 ,  H01L2225/06551 ,  H01L2225/06558 ,  H01L2225/06565 ,  H01L2225/1058 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01037 ,  H01L2924/0105 ,  H01L2924/01058 ,  H01L2924/01074 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/07802 ,  H01L2924/3511 ,  H01L2924/00014 ,  H01L2224/81 ,  H01L2224/83 ,  H01L2924/00 ,  H01L2221/68304

摘要： A layered chip package includes a main body, and wiring that includes a plurality of wires disposed on a side surface of the main body. The main body includes: a main part including first and second layer portions; and a plurality of first and second terminals that are disposed on the top and bottom surfaces of the main part, respectively, and are electrically connected to the plurality of wires. Each layer portion includes a semiconductor chip having a first surface and a second surface opposite thereto, and includes a plurality of electrodes. The electrodes are disposed on a side of the semiconductor chip opposite to the second surface. The first and second layer portions are bonded to each other such that the respective second surfaces face each other. The first terminals are formed by using the electrodes of the first layer portion, and the second terminals are formed by using the electrodes of the second layer portion.

摘要翻译： 分层芯片封装包括主体和布线，其包括布置在主体的侧表面上的多根导线。 主体包括：主要部分，包括第一和第二层部分; 以及多个第一和第二端子，其分别设置在主要部分的顶表面和底表面上，并且电连接到多个导线。 每个层部分包括具有第一表面和与其相对的第二表面的半导体芯片，并且包括多个电极。 电极设置在与第二表面相对的半导体芯片的一侧上。 第一和第二层部分彼此接合，使得相应的第二表面彼此面对。 通过使用第一层部分的电极形成第一端子，并且通过使用第二层部分的电极形成第二端子。

公开(公告)号：US08514520B2

公开(公告)日：2013-08-20

申请号：US13088852

申请日：2011-04-18

申请人： Yoshitaka Sasaki ,  Hiroyuki Ito ,  Shigeki Tanemura ,  Kazuki Sato ,  Atsushi Iijima

发明人： Yoshitaka Sasaki ,  Hiroyuki Ito ,  Shigeki Tanemura ,  Kazuki Sato ,  Atsushi Iijima

IPC分类号： G11B5/11 ,  G11B5/147 ,  G11B5/187

CPC分类号： G11B5/1278 ,  G11B5/3146 ,  G11B5/3163 ,  G11B5/3967 ,  Y10T29/49032

摘要： A thin-film magnetic head is constructed such that a main magnetic pole layer, a write shield layer, a gap layer, and a thin-film coil are laminated on a substrate. The write shield layer has an opposing shield part opposing the main magnetic pole layer and a front shield part. The front shield part is connected to the opposing shield part without straddling the thin-film coil. Besides, the front shield part has a shield front end face disposed in the medium-opposing surface and a shield upper end face formed distanced from the medium-opposing surface. Further, the front shield part has a shield connecting part. The shield front end face is connected to the shield upper end face by the shield connecting part.

摘要翻译： 薄膜磁头被构造为使得主磁极层，写入屏蔽层，间隙层和薄膜线圈层叠在基板上。 写屏蔽层具有与主磁极层相对的相对的屏蔽部分和前屏蔽部分。 前屏蔽部分连接到相对的屏蔽部分而不跨越薄膜线圈。 此外，前屏蔽部分具有设置在介质相对表面中的屏蔽前端面和远离介质相对表面形成的屏蔽上端面。 此外，前屏蔽部具有屏蔽连接部。 屏蔽前端面通过屏蔽连接部与屏蔽上端面连接。