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    Method of depositing a diffusion barrier layer and a metal conductive layer
    102.
    发明申请
    Method of depositing a diffusion barrier layer and a metal conductive layer 审中-公开
    沉积扩散阻挡层和金属导电层的方法

    公开(公告)号：US20050020080A1

    公开(公告)日：2005-01-27

    申请号：US10922052

    申请日：2004-08-18

    申请人： Tony Chiang ,  Gongda Yao ,  Peijun Ding ,  Fusen Chen ,  Barry Chin ,  Gene Kohara ,  Zheng Xu ,  Hong Zhang

    发明人： Tony Chiang ,  Gongda Yao ,  Peijun Ding ,  Fusen Chen ,  Barry Chin ,  Gene Kohara ,  Zheng Xu ,  Hong Zhang

    IPC分类号： H01L21/285 ,  H01L21/768 ,  H01L21/4763 ,  H01L21/302 ,  H01L21/461

    CPC分类号： H01L21/76843 ,  C23C14/046 ,  C23C14/165 ,  H01L21/2855 ,  H01L21/76805 ,  H01L21/76844 ,  H01L21/76846 ,  H01L21/76862 ,  H01L21/76865 ,  H01L21/76871 ,  H01L21/76877 ,  H01L21/76879 ,  H01L21/76883

    摘要： We disclose a method of applying a sculptured layer of material on a semiconductor feature surface using ion deposition sputtering, wherein a surface onto which the sculptured layer is applied is protected to resist erosion and contamination by impacting ions of a depositing layer, said method comprising the steps of: a) applying a first portion of a sculptured layer with sufficiently low substrate bias that a surface onto which said sculptured layer is applied is not eroded away or contaminated in an amount which is harmful to said semiconductor device performance or longevity; and b) applying a subsequent portion of said sculptured layer with sufficiently high substrate bias to sculpture a shape from said the first portion, while depositing additional layer material. The method is particularly applicable to the sculpturing of barrier layers, wetting layers, and conductive layers upon semiconductor feature surfaces and is especially helpful when the conductive layer is copper. In the application of a barrier layer, a first portion of barrier layer material is deposited on the substrate surface using standard sputtering techniques or using all ion deposition plasma, but in combination with sufficiently low substrate bias voltage (including at no applied substrate voltage) that the surfaces impacted by ions are not sputtered in an amount which is harmful to device performance or longevity. Subsequently, a second portion of barrier material is applied using ion deposition sputtering at increased substrate bias voltage which causes resputtering (sculpturing) or the first portion of barrier layer material, while enabling a more anisotropic deposition of newly depositing material. A conductive material, and particularly a copper seed layer applied to the feature may be accomplished using the same sculpturing technique as that described above with reference to the barrier layer.

    摘要翻译： 我们公开了使用离子沉积溅射在半导体特征表面上施加雕刻层的材料的方法，其中施加有雕刻层的表面被保护以通过冲击沉积层的离子来抵抗侵蚀和污染，所述方法包括 步骤：a）以足够低的衬底偏压施加雕刻层的第一部分，使得施加所述雕刻层的表面不会以对所述半导体器件的性能或寿命有害的量被侵蚀或污染; 以及b）将所述雕刻层的后续部分施加足够高的衬底偏压，以从所述第一部分雕刻形状，同时沉积附加层材料。 该方法特别适用于在半导体特征表面上雕刻阻挡层，润湿层和导电层，并且当导电层是铜时尤其有用。 在施加阻挡层时，使用标准溅射技术或使用所有离子沉积等离子体将阻挡层材料的第一部分沉积在衬底表面上，但是与足够低的衬底偏置电压（包括没有施加的衬底电压）相结合， 受离子影响的表面不会以对器件性能或寿命有害的量溅射。 随后，使用离子沉积溅射以增加的衬底偏置电压施加阻挡材料的第二部分，其引起再溅射（雕刻）或阻挡层材料的第一部分，同时能够进行更多的各向异性沉积新沉积材料。 应用于特征的导电材料，特别是铜种子层可以使用与上述参考阻挡层所述相同的雕刻技术来实现。

    Damage-free sculptured coating deposition
    103.
    发明授权
    Damage-free sculptured coating deposition 有权
    无损伤雕刻涂层沉积

    公开(公告)号：US06758947B2

    公开(公告)日：2004-07-06

    申请号：US09886439

    申请日：2001-06-20

    申请人： Tony Chiang ,  Gongda Yao ,  Peijun Ding ,  Fusen E. Chen ,  Barry L. Chin ,  Gene Y. Kohara ,  Zheng Xu ,  Hong Zhang

    发明人： Tony Chiang ,  Gongda Yao ,  Peijun Ding ,  Fusen E. Chen ,  Barry L. Chin ,  Gene Y. Kohara ,  Zheng Xu ,  Hong Zhang

    IPC分类号： C23C1400

    CPC分类号： H01L21/76843 ,  C23C14/046 ,  C23C14/165 ,  H01L21/2855 ,  H01L21/76805 ,  H01L21/76844 ,  H01L21/76846 ,  H01L21/76862 ,  H01L21/76865 ,  H01L21/76871 ,  H01L21/76877 ,  H01L21/76879 ,  H01L21/76883

    摘要： We disclose a method of applying a sculptured layer of material on a semiconductor feature surface using ion deposition sputtering, wherein a surface onto which the sculptured layer is applied is protected to resist erosion and contamination by impacting ions of a depositing layer. A first protective layer of material is deposited on a substrate surface using traditional sputtering or ion deposition sputtering, in combination with sufficiently low substrate bias that a surface onto which the layer is applied is not eroded away or contaminated during deposition of the protective layer. Subsequently, a sculptured second layer of material is applied using ion deposition sputtering at an increased substrate bias, to sculpture a shape from a portion of the first protective layer of material and the second layer of depositing material. The method is particularly applicable to the sculpturing of barrier layers, wetting layers, and conductive layers upon semiconductor feature surfaces.

    摘要翻译： 我们公开了使用离子沉积溅射在半导体特征表面上施加雕刻的材料层的方法，其中施加有雕刻层的表面被保护以通过冲击沉积层的离子来抵抗侵蚀和污染。 使用传统的溅射或离子沉积溅射将第一保护层材料沉积在衬底表面上，结合足够低的衬底偏压，使得施加层的表面在保护层沉积期间不被腐蚀掉或被污染。 随后，使用离子沉积溅射在增加的衬底偏压下施加雕刻的第二材料层，以从材料的第一保护层的一部分和第二沉积材料层的一部分雕刻出形状。 该方法特别适用于在半导体特征表面上雕刻阻挡层，润湿层和导电层。

    Computer system to control multiple step ionized metal plasma deposition process for conformal step coverage
    106.
    发明授权
    Computer system to control multiple step ionized metal plasma deposition process for conformal step coverage 失效
    计算机系统，用于控制多级电离金属等离子体沉积工艺，以保证适形阶梯覆盖

    公开(公告)号：US06449525B1

    公开(公告)日：2002-09-10

    申请号：US09558457

    申请日：2000-04-25

    申请人： Joanna Liu ,  Zheng Xu

    发明人： Joanna Liu ,  Zheng Xu

    IPC分类号： G06F1900

    CPC分类号： C23C14/35 ,  C23C14/046 ,  C23C14/345 ,  C23C14/3471 ,  C23C14/3492 ,  H01L21/2855 ,  H01L21/76843

    摘要： A multiple step process sputter deposits material of uniform thickness on stepped surfaces of an integrated circuit substrate such as the surfaces of a high aspect ratio via or a narrow trench. Material is first sputter deposited at the bottom of the opening at high pressure using a high power RF source connected to a coil in the deposition chamber to couple energy into the plasma. A high power RF bias is applied to the substrate, and a low power DC bias is applied to the sputtering target. The same parameters are repeated in a second step except that the high power RF bias on the substrate support is either reduced to a low power level or reduced to zero (by the end of the second step) to deposit on the lowest quarter of the sidewall of the opening. In a third step, no RF bias is applied to the pedestal remains and the pressure is reduced to a medium pressure state, resulting in a deposition on the second quarter of the sidewall of the opening. In a fourth step, the RF power coupled to the plasma is reduced to a low level, resulting in deposition on the third quarter of sidewall of the opening. Finally, the last quarter of the sidewall of the opening is deposited upon by lowering the pressure further to a low pressure state and applying a high power DC bias to the target.

    摘要翻译： 多步骤工艺在诸如高纵横比通孔或窄沟槽的表面的集成电路基板的台阶表面上溅射沉积具有均匀厚度的材料。 首先使用连接到沉积室中的线圈的高功率RF源在高压下在开口的底部溅射沉积材料，以将能量耦合到等离子体中。 向衬底施加高功率RF偏压，并且向溅射靶施加低功率DC偏压。 在第二步骤中重复相同的参数，除了衬底支撑件上的高功率RF偏压被降低到低功率水平或者减小到零（到第二步骤结束）以沉积在侧壁的最低四分之一上 的开幕。 在第三步骤中，没有RF偏压施加到基座保持件并且压力降低到中等压力状态，导致在开口的侧壁的第二个四分之一上的沉积。 在第四步骤中，耦合到等离子体的RF功率被降低到低水平，导致在开口的侧壁的第三季度上沉积。 最后，通过将压力进一步降低到低压状态并向目标施加高功率DC偏压来沉积开口侧壁的最后四分之一。

    Pulsed sputtering with a small rotating magnetron
    107.
    发明授权
    Pulsed sputtering with a small rotating magnetron 有权
    用小旋转磁控管进行脉冲溅射

    公开(公告)号：US06413382B1

    公开(公告)日：2002-07-02

    申请号：US09705324

    申请日：2000-11-03

    申请人： Wei Wang ,  Praburam Gopalraja ,  Jianming Fu ,  Zheng Xu

    发明人： Wei Wang ,  Praburam Gopalraja ,  Jianming Fu ,  Zheng Xu

    IPC分类号： C23C1435

    CPC分类号： H01J37/3444 ,  H01J37/3408 ,  H01J37/3455

    摘要： A magnetron sputter reactor having a target that is pulsed with a duty cycle of less than 10% and preferably less than 1% and further having a small magnetron of area less than 20% of the target area rotating about the target center, whereby a very high plasma density is produced during the pulse adjacent to the area of the magnetron. The power pulsing frequency needs to be desynchronized from the rotation frequency so that the magnetron does not overlie the same area of the magnetron during different pulses. Advantageously, the power pulses are delivered above a DC background level sufficient to continue to excite the plasma so that no ignition is required for each pulse.

    摘要翻译： 一种磁控溅射反应器，其具有以小于10％且优选小于1％的占空比脉冲的靶，并且还具有面积小于目标区域围绕目标中心旋转的20％的面积的小磁控管，由此非常 在与磁控管区域相邻的脉冲期间产生高等离子体密度。 功率脉冲频率需要与旋转频率不同步，从而磁控管在不同脉冲期间不会覆盖磁控管的相同区域。 有利地，功率脉冲在DC背景水平之上传送足以继续激发等离子体，使得每个脉冲不需要点火。

    Method and apparatus for forming a uniform layer on a workpiece during sputtering
    108.
    发明授权
    Method and apparatus for forming a uniform layer on a workpiece during sputtering 失效
    溅射期间在工件上形成均匀层的方法和装置

    公开(公告)号：US06409890B1

    公开(公告)日：2002-06-25

    申请号：US09362917

    申请日：1999-07-27

    申请人： Howard E. Grunes ,  Zheng Xu ,  Praburam Gopalraja ,  John C. Forster ,  Ralf Hofmann ,  Anantha Subramani

    发明人： Howard E. Grunes ,  Zheng Xu ,  Praburam Gopalraja ,  John C. Forster ,  Ralf Hofmann ,  Anantha Subramani

    IPC分类号： C23C1435

    CPC分类号： H01J37/321 ,  C23C14/044 ,  C23C14/358 ,  H01J37/3447

    摘要： Embodiments include devices and methods for sputtering material onto a workpiece in a chamber which includes a plasma generation area and a target. A coil is positioned to inductively couple energy into the plasma generation area to generate a plasma. A body is positioned between the workpiece and the target to prevent an amount of target material from being sputtered onto the workpiece. The body prevents an amount of target material from being sputtered onto the workpiece. The body may act as a dark space shield and inhibit plasma formation between the body and the target. The body may also act as a physical shield to block sputtered material from accumulating on the workpiece.

    摘要翻译： 实施例包括用于在包括等离子体产生区域和靶子的室中将材料溅射到工件上的装置和方法。 线圈被定位成将能量感应地耦合到等离子体产生区域中以产生等离子体。 主体位于工件和目标之间，以防止一定量的目标材料溅射到工件上。 该主体防止一定量的目标材料溅射到工件上。 身体可以作为暗空间屏蔽，并且抑制身体和目标之间的血浆形成。 主体还可以作为物理屏蔽来阻止溅射的材料积聚在工件上。

    Method for low thermal budget metal filling and planarization of contacts vias and trenches
    110.
    发明授权
    Method for low thermal budget metal filling and planarization of contacts vias and trenches 失效
    用于低热预算金属填充和平面化接触通孔和沟槽半导体晶片的方法和装置

    公开(公告)号：US06313027B1

    公开(公告)日：2001-11-06

    申请号：US08944140

    申请日：1997-10-06

    申请人： Zheng Xu ,  John Forster ,  Tse-Yong Yao

    发明人： Zheng Xu ,  John Forster ,  Tse-Yong Yao

    IPC分类号： H01L214763

    CPC分类号： H01L21/2855 ,  C23C14/0036 ,  C23C14/046 ,  C23C14/0641 ,  C23C14/32 ,  C23C14/358 ,  H01J37/34 ,  H01J2237/32 ,  H01L21/28518 ,  H01L21/76846 ,  H01L21/76876 ,  H01L21/76877 ,  H01L21/76882 ,  H01L23/485 ,  H01L23/5226 ,  H01L23/53223 ,  H01L23/53233 ,  H01L23/53238 ,  H01L2924/0002 ,  H01L2924/00

    摘要： The present invention pertains to a carrier layer and a contact enabled by the carrier layer which enables the fabrication of aluminum (including aluminum alloys and other conductive materials having a similar melting point) electrical contacts in multilayer integrated circuit vias, through holes, or trenches having an aspect ratio greater than one. In fact, the structure has been shown to enable such contact fabrication in vias, through holes, and trenches having aspect ratios as high as at least 5:1, and should be capable of filing apertures having aspect ratios up to about 12:1. The carrier layer, in addition to permitting the formation of a conductive contact at high aspect ratio, provides a diffusion barrier which prevents the aluminum from migrating into surrounding substrate material which operates in conjunction with the electrical contact. The carrier layer preferably comprises a layer formed by ionizing the flux of sputter deposition material, partially reacting the flux with a gas, and depositing the resulting material on a substrate.

    摘要翻译： 本发明涉及载体层和由载体层实现的接触，其能够在多层集成电路通孔，通孔或沟槽中制造具有类似熔点的铝（包括铝合金和具有相似熔点的其它导电材料）电接触，所述多层集成电路通孔，通孔或沟槽具有 长宽比大于1。 事实上，已经显示了这种结构能够使通孔，通孔和沟槽中的这种接触制造具有高达至少5:1的纵横比，并且应该能够填充具有高达约12:1的纵横比的孔。 除了允许以高纵横比形成导电接触之外，载体层提供了扩散阻挡层，其防止铝迁移到与电触点一起操作的周围基底材料中。 载体层优选包括通过电离溅射沉积材料的焊剂形成的层，使焊剂与气体部分地反应，并将所得材料沉积在衬底上。