公开(公告)号：US20200273824A1

公开(公告)日：2020-08-27

申请号：US16369836

申请日：2019-03-29

Applicant: Intel Corporation

Inventor： Telesphor Kamgaing ,  Georgios Dogiamis ,  Hyung-Jin Lee ,  Henning Braunisch ,  Richard Dischler

IPC: H01L23/66 ,  H01L23/00 ,  H01L21/48

Abstract: Embodiments may relate to a microelectronic package that includes a package substrate and a signal interconnect coupled with the face of the package substrate. The microelectronic package may further include a ground interconnect coupled with the face of the package substrate. The ground interconnect may at least partially surround the signal interconnect. Other embodiments may be described or claimed.

公开(公告)号：US10381291B2

公开(公告)日：2019-08-13

申请号：US15745701

申请日：2015-09-25

Applicant: Intel Corporation

Inventor： Adel A. Elsherbini ,  Henning Braunisch ,  Brandon M. Rawlings ,  Aleksandar Aleksov ,  Feras Eid ,  Javier Soto

IPC: H01L23/48 ,  H01L21/48 ,  H01L21/768 ,  H01L23/522 ,  H01L23/532

Abstract: Embodiments of the invention include conductive vias and methods for forming the conductive vias. In one embodiment, a via pad is formed over a first dielectric layer and a photoresist layer is formed over the first dielectric layer and the via pad. Embodiments may then include patterning the photoresist layer to form a via opening over the via pad and depositing a conductive material into the via opening to form a via over the via pad. Embodiments may then includeremoving the photoresist layer and forming a second dielectric layer over the first dielectric layer, the via pad, and the via. For example a top surface of the second dielectric layer is formed above a top surface of the via in some embodiments. Embodiments may then include recessing the second dielectric layer to expose a top portion of the via.

公开(公告)号：US10304686B2

公开(公告)日：2019-05-28

申请号：US15476842

申请日：2017-03-31

Applicant: INTEL CORPORATION

Inventor： Sasha N. Oster ,  Fay Hua ,  Telesphor Kamgaing ,  Adel A. Elsherbini ,  Henning Braunisch ,  Johanna M. Swan

IPC: H01L21/4763 ,  H01L21/285 ,  H01L21/768 ,  H01L21/033 ,  B82Y40/00

Abstract: Embodiments include devices and methods, including a method for processing a substrate. The method includes providing a substrate including a first portion and a second portion, the first portion including a feature, the feature including an electrically conductive region, the second portion including a dielectric surface region. The method also includes performing self-assembled monolayer (SAM) assisted structuring plating to form a structure comprising a metal on the dielectric surface region, the feature being formed using a process other than the SAM assisted structuring plating used to form the structure, and the structure being formed after the feature. Other embodiments are described and claimed.

公开(公告)号：US20190097293A1

公开(公告)日：2019-03-28

申请号：US16186103

申请日：2018-11-09

Applicant: Intel Corporation

Inventor： Georgios Dogiamis ,  Adel A. Elsherbini ,  Henning Braunisch ,  Gilbert W. Dewey ,  Telesphor Kamgaing ,  Hyung-Jin Lee ,  Johanna M. Swan

IPC: H01P3/127 ,  H01P3/10 ,  H01P5/103

Abstract: There is disclosed in one example an electromagnetic wave launcher apparatus, including: an interface to an electromagnetic waveguide; a first launcher configured to launch a high-frequency electromagnetic signal onto a first cross-sectional portion of the waveguide; and a second launcher configured to launch a lower-frequency electromagnetic signal onto a second cross-sectional portion of the waveguide.

公开(公告)号：US20190096798A1

公开(公告)日：2019-03-28

申请号：US15718012

申请日：2017-09-28

Applicant: Intel Corporation

Inventor： Aleksandar Aleksov ,  Arnab Sarkar ,  Arghya Sain ,  Kristof Darmawikarta ,  Henning Braunisch ,  Prashant D. Parmar ,  Sujit Sharan ,  Johanna M. Swan ,  Feras Eid

IPC: H01L23/50 ,  H01L21/48 ,  H01L23/498

CPC classification number: H01L23/50 ,  G06F17/5068 ,  G06F17/5077 ,  G06F2217/40 ,  H01L21/4853 ,  H01L21/486 ,  H01L23/49816 ,  H01L23/49827 ,  H01L23/49838 ,  H01L23/49866 ,  H01L23/5225 ,  H01L23/5226 ,  H01L23/5286 ,  H01L24/05 ,  H01L24/13 ,  H01L24/16 ,  H01L2224/0401 ,  H01L2224/05083 ,  H01L2224/05144 ,  H01L2224/05147 ,  H01L2224/05164 ,  H01L2224/13022 ,  H01L2224/131 ,  H01L2224/16145 ,  H01L2924/1434 ,  H01L2924/15311 ,  H01L2924/3011 ,  H01L2924/014 ,  H01L2924/00014

Abstract: Aspects of the embodiments are directed to an IC chip that includes a substrate comprising a first metal layer, a second metal layer, and a ground plane residing on the first metal layer. The second metal layer can include a first signal trace, the first signal trace electrically coupled to a first signal pad residing in the first metal layer by a first signal via. The second metal layer can include a second signal trace, the second signal trace electrically coupled to a second signal pad residing in the first metal layer by a second signal via. The substrate can also include a ground trace residing in the second metal layer between the first signal trace and the second signal trace, the ground trace electrically coupled to the ground plane by a ground via. The vias coupled to the traces can include self-aligned or zero-misaligned vias.

公开(公告)号：US09713264B2

公开(公告)日：2017-07-18

申请号：US14576107

申请日：2014-12-18

Applicant: Intel Corporation

Inventor： Brandon M. Rawlings ,  Henning Braunisch

IPC: H05K3/00 ,  H05K3/46 ,  H05K1/11 ,  H05K3/42

CPC classification number: H05K3/0082 ,  H05K1/116 ,  H05K3/422 ,  H05K3/424 ,  H05K3/4647 ,  H05K3/4679 ,  H05K2201/09463 ,  H05K2201/09854 ,  H05K2203/0505

Abstract: A photoresist is deposited on a seed layer on a substrate. A first region of the photoresist is removed to expose a first portion of the seed layer to form a via-pad structure. A first conductive layer is deposited onto the first portion of the seed layer. A second region of the photoresist adjacent to the first region is removed to expose a second portion of the seed layer to form a line. A second conductive layer is deposited onto the first conductive layer and the second portion of the seed layer.

公开(公告)号：US12199067B2

公开(公告)日：2025-01-14

申请号：US17222815

申请日：2021-04-05

Applicant: Intel Corporation

Inventor： Adel A. Elsherbini ,  Henning Braunisch ,  Javier Soto Gonzalez ,  Shawna M. Liff

IPC: H01L23/00 ,  H01L23/538 ,  H01L25/065

Abstract: An embedded silicon bridge system including tall interconnect via pillars is part of a system in package device. The tall via pillars may span a Z-height distance to a subsequent bond pad from a bond pad that is part of an organic substrate that houses the embedded silicon bridge.

公开(公告)号：US20250006781A1

公开(公告)日：2025-01-02

申请号：US18344695

申请日：2023-06-29

Applicant: Intel Corporation

Inventor： Thomas Sounart ,  Henning Braunisch ,  Aleksandar Aleksov ,  Kristof Darmawikarta ,  Darko Grujicic ,  Marcel Wall ,  Suddhasattwa Nad ,  Benjamin Duong ,  Shayan Kaviani

IPC: H01G4/012 ,  H01L21/48 ,  H01L23/498

Abstract: Carbon nanofiber capacitor apparatus and related methods are disclosed herein. An example apparatus includes an integrated circuit package substrate, and a capacitor provided in the integrated circuit package substrate. The capacitor includes a carbon fiber array, a dielectric film positioned on the carbon fiber array, and an electrode film positioned on the dielectric film.

公开(公告)号：US12170244B2

公开(公告)日：2024-12-17

申请号：US16914062

申请日：2020-06-26

Applicant: Intel Corporation

Inventor： Adel Elsherbini ,  Feras Eid ,  Georgios Dogiamis ,  Henning Braunisch ,  Beomseok Choi ,  William J. Lambert ,  Stephen Morein ,  Ahmed Abou-Alfotouh ,  Johanna Swan

IPC: H01L23/522 ,  H01L21/768 ,  H01L23/532 ,  H05K1/11 ,  H05K3/14

Abstract: An integrated circuit (IC) die package substrate comprises a first trace upon, or embedded within, a dielectric material. The first trace comprises a first metal and a first via coupled to the first trace. The first via comprises the first metal and a second trace upon, or embedded within, the dielectric material. A second via is coupled to the second trace, and at least one of the second trace or the second via comprises a second metal with a different microstructure or composition than the first metal.

公开(公告)号：US20240355725A1

公开(公告)日：2024-10-24

申请号：US18762484

申请日：2024-07-02

Applicant: Intel Corporation

Inventor： Adel Elsherbini ,  Feras Eid ,  Georgios Dogiamis ,  Beomseok Choi ,  Henning Braunisch ,  William Lambert ,  Krishna Bharath ,  Johanna Swan

IPC: H01L23/50 ,  H01L21/48 ,  H01L21/56 ,  H01L23/00 ,  H01L23/31 ,  H01L23/367 ,  H01L23/48 ,  H01L25/00 ,  H01L25/065 ,  H05K1/18

CPC classification number: H01L23/50 ,  H01L21/4853 ,  H01L21/563 ,  H01L23/3185 ,  H01L23/367 ,  H01L23/481 ,  H01L23/562 ,  H01L24/16 ,  H01L25/0657 ,  H01L25/50 ,  H05K1/181 ,  H01L2224/16227 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06541 ,  H01L2225/06565 ,  H01L2924/18161

Abstract: An integrated circuit assembly may be fabricated having an electronic substrate, an integrated circuit device having a first surface, an opposing second surface, at least one side extending between the first surface and the second surface, and at least one through-substrate via extending into the integrated circuit device from the second surface, wherein the first surface of the integrated circuit device is electrically attached to the electronic substrate; and at least one power delivery route electrically attached to the second surface of the integrated circuit device and to the electronic substrate, wherein the at least one power delivery route is conformal to the side of the integrated circuit device and the first surface of the electronic substrate.