公开(公告)号：US20190148533A1

公开(公告)日：2019-05-16

申请号：US16242949

申请日：2019-01-08

Applicant: Intel Corporation

Inventor： Marko RADOSAVLJEVIC ,  Sansaptak DASGUPTA ,  Sanaz K. GARDNER ,  Seung Hoon SUNG ,  Han Wui THEN ,  Robert S. CHAU

IPC: H01L29/778 ,  H01L29/08 ,  H01L29/66 ,  H01L21/02 ,  H01L29/06 ,  H01L29/205 ,  H01L21/8258

CPC classification number: H01L29/7786 ,  H01L21/02381 ,  H01L21/02488 ,  H01L21/02513 ,  H01L21/0254 ,  H01L21/02647 ,  H01L21/823431 ,  H01L21/8252 ,  H01L21/8258 ,  H01L29/0657 ,  H01L29/0847 ,  H01L29/0891 ,  H01L29/2003 ,  H01L29/205 ,  H01L29/66462

Abstract: Semiconductor devices including an elevated or raised doped crystalline structure extending from a device layer are described. In embodiments, III-N transistors include raised crystalline n+ doped source/drain structures on either side of a gate stack. In embodiments, an amorphous material is employed to limit growth of polycrystalline source/drain material, allowing a high quality source/drain doped crystal to grow from an undamaged region and laterally expand to form a low resistance interface with a two-degree electron gas (2DEG) formed within the device layer. In some embodiments, regions of damaged GaN that may spawn competitive polycrystalline overgrowths are covered with the amorphous material prior to commencing raised source/drain growth.

公开(公告)号：US20190131437A1

公开(公告)日：2019-05-02

申请号：US16095655

申请日：2016-06-30

Applicant: Intel Corporation

Inventor： Van Hoang LE ,  Gilbert William DEWEY ,  Marko RADOSAVLJEVIC ,  Rafael RIOS ,  Jack T. KAVALIEROS

IPC: H01L29/66 ,  H01L27/12 ,  H01L29/78 ,  H01L29/06 ,  H01L29/24

Abstract: Integrated circuit dies having multi-gate, non-planar transistors built into a back-end-of-line portion of the die are described. In an example, non-planar transistors include an amorphous oxide semiconductor (AOS) channel extending between a source module and a drain module. A gate module may extend around the AOS channel to control electrical current flow between the source module and the drain module. The AOS channel may include an AOS layer having indium gallium zinc oxide.

公开(公告)号：US20190131187A1

公开(公告)日：2019-05-02

申请号：US16094452

申请日：2016-06-28

Applicant: Intel Corporation

Inventor： Van H. LE ,  Marko RADOSAVLJEVIC ,  Benjamin CHU-KUNG ,  Rafael RIOS ,  Gilbert DEWEY

IPC: H01L21/84 ,  H01L27/12 ,  H01L21/768 ,  H01L23/522

Abstract: A monocrystalline semiconductor layer is formed on a conductive layer on an insulating layer on a substrate. The conductive layer is a part of an interconnect layer. The monocrystalline semiconductor layer extends laterally on the insulating layer. Other embodiments may be described and/or claimed.

公开(公告)号：US20180366587A1

公开(公告)日：2018-12-20

申请号：US15777117

申请日：2015-12-23

Applicant: Intel Corporation

Inventor： Van H. LE ,  Gilbert DEWEY ,  Rafael RIOS ,  Jack T. KAVALIEROS ,  Marko RADOSAVLJEVIC ,  Kent E. MILLARD ,  Marc C. FRENCH ,  Ashish AGRAWAL ,  Benjamin CHU-KUNG ,  Ryan E. ARCH

IPC: H01L29/786 ,  H01L29/06 ,  H01L29/24 ,  H01L29/423 ,  H01L29/49 ,  H01L21/02 ,  H01L29/40 ,  H01L29/66

Abstract: Embodiments of the invention include non-planar InGaZnO (IGZO) transistors and methods of forming such devices. In an embodiment, the IGZO transistor may include a substrate and source and drain regions formed over the substrate. According to an embodiment, an IGZO layer may be formed above the substrate and may be electrically coupled to the source region and the drain region. Further embodiments include a gate electrode that is separated from the IGZO layer by a gate dielectric. In an embodiment, the gate dielectric contacts more than one surface of the IGZO layer. In one embodiment, the IGZO transistor is a finfet transistor. In another embodiment the IGZO transistor is a nanowire or a nanoribbon transistor. Embodiments of the invention may also include a non-planar IGZO transistor that is formed in the back end of line stack (BEOL) of an integrated circuit chip.

公开(公告)号：US20180350985A1

公开(公告)日：2018-12-06

申请号：US15779070

申请日：2015-12-24

Applicant: INTEL CORPORATION

Inventor： Sansaptak DASGUPTA ,  Han Wui THEN ,  Marko RADOSAVLJEVIC

IPC: H01L29/78 ,  H01L29/08 ,  H01L29/16 ,  H01L29/20 ,  H01L29/267 ,  H01L27/092 ,  H01L29/66 ,  H01L21/02 ,  H01L21/8238

CPC classification number: H01L29/7848 ,  H01L21/0254 ,  H01L21/02645 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/823821 ,  H01L21/8258 ,  H01L27/092 ,  H01L27/0924 ,  H01L29/045 ,  H01L29/0847 ,  H01L29/16 ,  H01L29/2003 ,  H01L29/205 ,  H01L29/267 ,  H01L29/66522 ,  H01L29/66545 ,  H01L29/66636 ,  H01L29/66795 ,  H01L29/7851

Abstract: Transistors including doped heteroepitaxial III-N source/drain crystals. In embodiments, transistors including a group IV or group III-V channel crystal employ n+ doped III-N source/drain structures on either side of a gate stack. Lateral tensile strain of the channel crystal may result from lattice mismatch between the channel crystal and the III-N source/drain crystals. In embodiments, an amorphous material is employed to limit growth of III-N material to only a single channel crystal facet, allowing a high quality monocrystalline source/drain to form that is capable of sustaining significant stress. In some embodiments, an n+ III-N source/drain crystal is grown on a (110) or (111) surface of a silicon channel crystal fabricated into a fin structure to form a tensile strained NMOS finFET.

公开(公告)号：US20180315659A1

公开(公告)日：2018-11-01

申请号：US15528031

申请日：2014-12-17

Applicant: Intel Corporation

Inventor： Sansaptak DASGUPTA ,  Han Wui THEN ,  Marko RADOSAVLJEVIC ,  Sanaz K. GARDNER ,  Seung Hoon SUNG ,  Robert S. CHAU ,  Ravi PILLARISETTY

IPC: H01L21/8252 ,  H01L33/00 ,  H01L33/08 ,  H01L33/12 ,  H01L33/24 ,  H01L33/32

CPC classification number: H01L21/8252 ,  H01L21/02458 ,  H01L21/0254 ,  H01L21/0262 ,  H01L21/02639 ,  H01L21/02647 ,  H01L33/007 ,  H01L33/08 ,  H01L33/10 ,  H01L33/12 ,  H01L33/24 ,  H01L33/32 ,  H01L2224/16225 ,  H01L2924/15311

Abstract: Embodiments of the present disclosure are directed toward an integrated circuit (IC) die. In embodiments, an IC die may include a semiconductor substrate and a buffer layer disposed over the semiconductor substrate. The buffer layer may have a plurality of openings formed therein. In embodiments, the IC die may further include a plurality of group III-Nitride structures. Individual group III-Nitride structures of the plurality of group III-Nitride structures may include a lower portion disposed in a respective opening of the plurality of openings and an upper portion disposed over the respective opening. In embodiments, the upper portion may include a base extending radially from sidewalls of the respective opening over a surface of the buffer layer to form a perimeter around the respective opening. Other embodiments may be described and/or claimed.

公开(公告)号：US20170352532A1

公开(公告)日：2017-12-07

申请号：US15527287

申请日：2014-12-17

Applicant: Intel Corporation

Inventor： Sansaptak DASGUPTA ,  Han Wui THEN ,  Marko RADOSAVLJEVIC ,  Robert S. CHAU ,  Sanaz K. GARDNER ,  Seung Hoon SUNG

IPC: H01L21/02 ,  H01L21/027 ,  H01L21/8258 ,  H01L27/06 ,  H01L29/06 ,  H01L29/66 ,  H01L29/32 ,  H01L29/225 ,  H01L29/205 ,  H01L29/20 ,  H01L29/08 ,  H01L29/778 ,  H01L29/22 ,  H01L27/092 ,  H01L23/00

CPC classification number: H01L21/0265 ,  H01L21/02381 ,  H01L21/02458 ,  H01L21/0254 ,  H01L21/02551 ,  H01L21/02554 ,  H01L21/02557 ,  H01L21/0256 ,  H01L21/02562 ,  H01L21/0262 ,  H01L21/02639 ,  H01L21/02642 ,  H01L21/02647 ,  H01L21/0274 ,  H01L21/8258 ,  H01L23/48 ,  H01L24/16 ,  H01L25/065 ,  H01L27/0605 ,  H01L27/092 ,  H01L27/0922 ,  H01L29/0657 ,  H01L29/0688 ,  H01L29/0847 ,  H01L29/2003 ,  H01L29/205 ,  H01L29/2203 ,  H01L29/225 ,  H01L29/267 ,  H01L29/32 ,  H01L29/66462 ,  H01L29/66969 ,  H01L29/7786 ,  H01L2224/16227 ,  H01L2924/15311

Abstract: Embodiments of the present disclosure are directed towards an integrated circuit (IC) die. In embodiments, an IC die may include a semiconductor substrate, a group III-Nitride or II-VI wurtzite layer disposed over the semiconductor substrate, and a plurality of buffer structures at least partially embedded in the group III-Nitride or II-VI wurtzite layer. In some embodiments, each of the plurality of buffer structures may include a central member disposed over the semiconductor substrate, a lower lateral member disposed over the semiconductor substrate and extending laterally away from the central member, and an upper lateral member disposed over the central member and extending laterally from the central member in an opposite direction from the lower lateral member. The plurality of buffer structures may be positioned in a staggered arrangement to terminate defects of the group III-Nitride or II-VI wurtzite layer. Other embodiments may be described and/or claimed.

公开(公告)号：US20170323946A1

公开(公告)日：2017-11-09

申请号：US15656480

申请日：2017-07-21

Applicant: Intel Corporation

Inventor： Han Wui THEN ,  Sansaptak DASGUPTA ,  Marko RADOSAVLJEVIC ,  Benjamin CHU-KUNG ,  Sanaz GARDNER ,  Seung Hoon SUNG ,  Robert S. Chau

IPC: H01L29/20 ,  H01L21/02 ,  H01L29/78 ,  H01L29/778 ,  H01L29/66 ,  H01L29/423 ,  H01L29/201 ,  H01L29/06 ,  H01L27/12 ,  H01L21/84 ,  H01L21/285 ,  H01L21/283 ,  H01L29/80

CPC classification number: H01L29/2003 ,  H01L21/02164 ,  H01L21/02238 ,  H01L21/02255 ,  H01L21/0228 ,  H01L21/0254 ,  H01L21/283 ,  H01L21/28575 ,  H01L21/84 ,  H01L27/1203 ,  H01L29/0649 ,  H01L29/201 ,  H01L29/42356 ,  H01L29/66462 ,  H01L29/66795 ,  H01L29/7787 ,  H01L29/78 ,  H01L29/785 ,  H01L29/7851 ,  H01L29/802

Abstract: A III-N semiconductor channel is formed on a III-N transition layer formed on a (111) or (110) surface of a silicon template structure, such as a fin sidewall. In embodiments, the silicon fin has a width comparable to the III-N epitaxial film thicknesses for a more compliant seeding layer, permitting lower defect density and/or reduced epitaxial film thickness. In embodiments, a transition layer is GaN and the semiconductor channel comprises Indium (In) to increase a conduction band offset from the silicon fin. In other embodiments, the fin is sacrificial and either removed or oxidized, or otherwise converted into a dielectric structure during transistor fabrication. In certain embodiments employing a sacrificial fin, the III-N transition layer and semiconductor channel is substantially pure GaN, permitting a breakdown voltage higher than would be sustainable in the presence of the silicon fin.

公开(公告)号：US20170271448A1

公开(公告)日：2017-09-21

申请号：US15598290

申请日：2017-05-17

Applicant: Intel Corporation

Inventor： Benjamin CHU-KUNG ,  Sherry R. TAFT ,  Van H. LE ,  Sansaptak DASGUPTA ,  Seung Hoon SUNG ,  Sanaz K. GARDNER ,  Matthew V. METZ ,  Marko RADOSAVLJEVIC ,  Han Wui THEN

IPC: H01L29/10 ,  H01L29/06 ,  H01L29/161 ,  H01L29/66 ,  H01L29/20

CPC classification number: H01L29/1037 ,  H01L21/02381 ,  H01L21/0254 ,  H01L21/02639 ,  H01L29/0649 ,  H01L29/161 ,  H01L29/2003 ,  H01L29/66795 ,  H01L29/785

Abstract: Techniques are disclosed for forming a defect-free semiconductor structure on a dissimilar substrate with a multi-aspect ratio mask. The multi-aspect ratio mask comprises a first, second, and third layer formed on a substrate. The second layer has a second opening wider than a first opening and a third opening in the first and third layers, respectively. All three openings are centered along a common central axis. A semiconductor material is grown from the top surface of the substrate and laterally onto the top surface of the first layer within the second opening. The semiconductor material disposed within and vertically below the third opening is etched by using the third layer as an etch mask so that the remaining material that laterally overflowed onto the top surface of the first layer forms a remaining structure.

公开(公告)号：US20170012126A1

公开(公告)日：2017-01-12

申请号：US15119674

申请日：2014-03-28

Applicant: INTEL CORPORATION

Inventor： Benjamin CHU-KUNG ,  Gilbert DEWEY ,  Van H. LE ,  Jack T. KAVALIEROS ,  Marko RADOSAVLJEVIC ,  Ravi PILLARISETTY ,  Han Wui THEN ,  Niloy MUKHERJEE ,  Sansaptak DASGUPTA

IPC: H01L29/78 ,  H01L29/06 ,  H01L29/66 ,  H01L29/423 ,  H01L29/786

Abstract: Vertical semiconductor devices having selectively regrown top contacts and method of fabricating vertical semiconductor devices having selectively regrown top contacts are described. For example, a semiconductor device includes a substrate having a surface. A first source/drain region is disposed on the surface of the substrate. A vertical channel region is disposed on the first source/drain region and has a first width parallel with the surface of the substrate. A second source/drain region is disposed on the vertical channel region and has a second width parallel with and substantially greater than the first width. A gate stack is disposed on and completely surrounds a portion of the vertical channel region.

Abstract translation: 描述了具有选择性再生长顶端触点的垂直半导体器件和制造具有选择性再生长顶端触点的垂直半导体器件的方法。 例如，半导体器件包括具有表面的衬底。 第一源极/漏极区域设置在衬底的表面上。 垂直沟道区域设置在第一源极/漏极区域上并且具有与衬底的表面平行的第一宽度。 第二源极/漏极区域设置在垂直沟道区域上并且具有与第一宽度平行并且基本上大于第一宽度的第二宽度。 栅堆叠设置在垂直沟道区的一部分上并完全环绕。