中科微点-全球专利检索

  1. Login
  2. Sign Up

Search Results

125 records (took 0.026 seconds)

    THREE-DIMENSIONAL NANORIBBON-BASED HYSTERETIC MEMORY
    103.
    发明公开
    THREE-DIMENSIONAL NANORIBBON-BASED HYSTERETIC MEMORY 审中-公开

    公开(公告)号：US20230180482A1

    公开(公告)日：2023-06-08

    申请号：US17543809

    申请日：2021-12-07

    Applicant: Intel Corporation

    Inventor： Wilfred Gomes ,  Uygar E. Avci ,  Abhishek A. Sharma

    IPC: H01L27/11514 ,  H01L27/11504 ,  H01L29/06 ,  H01L29/423 ,  H01L29/786

    CPC classification number: H01L27/11514 ,  H01L27/11504 ,  H01L29/0665 ,  H01L29/42392 ,  H01L29/78618 ,  H01L29/78696

    Abstract: Three-dimensional hysteretic memory based on semiconductor nanoribbons is disclosed. An example memory cell may include a nanoribbon-based access transistor and a capacitor coupled to the access transistor, where the capacitor at least partially wraps around the nanoribbon in which the access transistor is formed. One or both of a gate stack of the access transistor and the capacitor insulator may include a hysteretic material/arrangement. Plurality of such memory cells may be provided in a single nanoribbon, and the nanoribbon may be one of a stack of nanoribbons provided above one another over a support structure. Incorporating hysteretic memory cells in different layers above a support structure by using stacks of semiconductor nanoribbons may allow significantly increasing density of hysteretic memory cells in a memory array having a given footprint area, or conversely, significantly reducing the footprint area of the memory array with a given density of hysteretic memory cells.

    Memory cell with a ferroelectric capacitor integrated with a transtor gate
    104.
    发明授权
    Memory cell with a ferroelectric capacitor integrated with a transtor gate 有权

    公开(公告)号：US11502103B2

    公开(公告)日：2022-11-15

    申请号：US16114272

    申请日：2018-08-28

    Applicant: Intel Corporation

    Inventor： Daniel H. Morris ,  Seiyon Kim ,  Uygar E. Avci ,  Ian A. Young

    IPC: G11C11/22 ,  H01L27/1159 ,  H01L29/78 ,  H01L21/28 ,  H01L29/51 ,  H01L29/66

    Abstract: Described herein are ferroelectric (FE) memory cells that include transistors having gates with FE capacitors integrated therein. An example memory cell includes a transistor having a semiconductor channel material, a gate dielectric over the semiconductor material, a first conductor material over the gate dielectric, a FE material over the first conductor material, and a second conductor material over the FE material. The first and second conductor materials form, respectively, first and second capacitor electrodes of a capacitor, where the first and second capacitor electrodes are separated by the FE material (hence, a “FE capacitor”). Separating a FE material from a semiconductor channel material of a transistor with a layer of a gate dielectric and a layer of a first conductor material eliminates the FE-semiconductor interface that may cause endurance issues in some other FE memory cells.

    Anti-ferroelectric capacitor memory cell
    106.
    发明授权
    Anti-ferroelectric capacitor memory cell 有权

    公开(公告)号：US11355504B2

    公开(公告)日：2022-06-07

    申请号：US15994227

    申请日：2018-05-31

    Applicant: Intel Corporation

    Inventor： Daniel H. Morris ,  Uygar E. Avci ,  Ian A. Young

    IPC: G11C11/22 ,  H01L27/11507 ,  H01L49/02

    Abstract: Described herein are anti-ferroelectric (AFE) memory cells and corresponding methods and devices. For example, in some embodiments, an AFE memory cell disclosed herein includes a capacitor employing an AFE material between two capacitor electrodes. Applying a voltage to one electrode of such capacitor allows boosting the charge at the other electrode, where nonlinear behavior of the AFE material between the two electrodes may advantageously manifest itself in that, for a given voltage applied to the first electrode, a factor by which the charge is boosted at the second electrode of the capacitor may be substantially different for different values of charge at that electrode before the boost. Connecting the second capacitor electrode to a storage node of the memory cell may then allow boosting the charge on the storage node so that different logic states of the memory cell become more clearly resolvable, enabling increased retention times.

    MULTI-LEVEL SPIN LOGIC
    109.
    发明申请
    MULTI-LEVEL SPIN LOGIC 有权

    公开(公告)号：US20210143819A1

    公开(公告)日：2021-05-13

    申请号：US17152552

    申请日：2021-01-19

    Applicant: Intel Corporation

    Inventor： Sasikanth Manipatruni ,  Ian A. Young ,  Dmitri E. Nikonov ,  Uygar E. Avci ,  Patrick Morrow ,  Anurag Chaudhry

    IPC: H03K19/00 ,  H01L43/04 ,  H01L43/06 ,  H01L43/10 ,  H03K19/18

    Abstract: Described is an apparatus which comprises: a 4-state input magnet; a first spin channel region adjacent to the 4-state input magnet; a 4-state output magnet; a second spin channel region adjacent to the 4-state input and output magnets; and a third spin channel region adjacent to the 4-state output magnet. Described in an apparatus which comprises: a 4-state input magnet; a first filter layer adjacent to the 4-state input magnet; a first spin channel region adjacent to the first filter layer; a 4-state output magnet; a second filter layer adjacent to the 4-state output magnet; a second spin channel region adjacent to the first and second filter layers; and a third spin channel region adjacent to the second filter layer.

Patent Agency Ranking