公开(公告)号：US10304498B2

公开(公告)日：2019-05-28

申请号：US16137309

申请日：2018-09-20

Applicant: Micron Technology, Inc.

Inventor： Toru Tanzawa

IPC: G11C16/10 ,  G11C5/06 ,  G11C16/26 ,  H01L27/11529 ,  H01L27/11551 ,  H01L27/11524 ,  G11C7/22 ,  G11C7/12 ,  G11C5/02 ,  G11C16/04 ,  G11C16/08 ,  G11C16/16

Abstract: Apparatuses and methods for interconnections for 3D memory are provided. One example apparatus can include a stack of materials including a plurality of pairs of materials, each pair of materials including a conductive line formed over an insulation material. The stack of materials has a stair step structure formed at one edge extending in a first direction. Each stair step includes one of the pairs of materials. A first interconnection is coupled to the conductive line of a stair step, the first interconnection extending in a second direction substantially perpendicular to a first surface of the stair step.

公开(公告)号：US20190147966A1

公开(公告)日：2019-05-16

申请号：US16228733

申请日：2018-12-20

Applicant: Micron Technology, Inc.

Inventor： Han Zhao ,  Akira Goda ,  Krishna K. Parat ,  Aurelio Giancarlo Mauri ,  Haitao Liu ,  Toru Tanzawa ,  Shigekazu Yamada ,  Koji Sakui

IPC: G11C16/34 ,  G11C16/06 ,  G11C16/16 ,  G11C16/04 ,  G11C16/26 ,  G11C16/08 ,  G11C16/32

Abstract: Some embodiments include apparatuses and methods having a memory cell string including memory cells located in different levels of the apparatus and a data line coupled to the memory cell string. The memory cell string includes a pillar body associated with the memory cells. At least one of such apparatus can include a module configured to store information in a memory cell among memory cells and/or to determine a value of information stored in a memory cell among memory cells. The module can also be configured to apply a voltage having a positive value to the data line and/or a source to control a potential of the body. Other embodiments are described.

公开(公告)号：US10282093B2

公开(公告)日：2019-05-07

申请号：US15722054

申请日：2017-10-02

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Toru Tanzawa

IPC: G06F3/06 ,  G06F13/16 ,  G06F12/06 ,  G06F12/14

Abstract: Methods of operating a memory include performing a memory access operation, obtaining an address corresponding to a subsequent memory access operation prior to stopping the memory access operation, stopping the memory access operation, sharing charge between access lines used for the memory access operation and access lines to be used for the subsequent memory access operation, and performing the subsequent memory access operation.

公开(公告)号：US20190087103A1

公开(公告)日：2019-03-21

申请号：US16197208

申请日：2018-11-20

Applicant: Micron Technology, Inc.

Inventor： Toru Tanzawa

IPC: G06F3/06 ,  G11C11/00 ,  H01L29/51 ,  G11C11/56 ,  G11C16/34 ,  G11C16/04 ,  H01L27/1157 ,  H01L27/11556 ,  H01L27/11524 ,  H01L27/11582

CPC classification number: G06F3/0613 ,  G06F3/0625 ,  G06F3/064 ,  G06F3/0656 ,  G06F3/0679 ,  G11C11/005 ,  G11C11/5628 ,  G11C11/5635 ,  G11C11/5642 ,  G11C11/5657 ,  G11C11/5671 ,  G11C16/0483 ,  G11C16/3459 ,  H01L27/11524 ,  H01L27/11556 ,  H01L27/1157 ,  H01L27/11582 ,  H01L27/1159 ,  H01L27/11597 ,  H01L29/516

Abstract: Some embodiments include apparatuses, and methods of forming and operating the apparatuses. Some of the apparatuses include a conductive line, non-volatile memory cells of a first memory cell type, the non-volatile memory cells coupled in series among each other, and an additional non-volatile memory cell of a second memory cell type coupled to the conductive line and coupled in series with the non-volatile memory cells of the first memory cell type. The second memory cell type is different from the first memory cell type.

公开(公告)号：US10224103B2

公开(公告)日：2019-03-05

申请号：US15019175

申请日：2016-02-09

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Toru Tanzawa

IPC: G11C16/04 ,  G11C11/00 ,  G11C16/10 ,  G11C16/26 ,  G11C16/34

Abstract: In an example, a memory device has a first string of memory cells selectively connected to a first data line, a second string of memory cells selectively connected to a second data line, and a transistor that selectively connects the first data line to the second data line, thereby permitting connecting the first and second data lines in series before programming or sensing memory cells of the first and second strings of memory cells.

公开(公告)号：US10203885B2

公开(公告)日：2019-02-12

申请号：US15408671

申请日：2017-01-18

Applicant: Micron Technology, Inc.

Inventor： Toru Tanzawa

IPC: G11C16/04 ,  G06F3/06 ,  G11C11/56 ,  G11C16/34 ,  H01L27/11524 ,  H01L27/11556 ,  H01L27/1157 ,  H01L27/11582 ,  H01L27/1159 ,  H01L27/11597

Abstract: Some embodiments include apparatuses, and methods of forming and operating the apparatuses. Some of the apparatuses include a conductive line, non-volatile memory cells of a first memory cell type, the non-volatile memory cells coupled in series among each other, and an additional non-volatile memory cell of a second memory cell type coupled to the conductive line and coupled in series with the non-volatile memory cells of the first memory cell type. The second memory cell type is different from the first memory cell type.

公开(公告)号：US20190035472A1

公开(公告)日：2019-01-31

申请号：US16148405

申请日：2018-10-01

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Qiang Tang ,  Ramin Ghodsi ,  Toru Tanzawa

IPC: G11C16/10 ,  G11C16/04 ,  G11C16/34 ,  G11C16/26 ,  G11C11/56 ,  G11C16/08 ,  G11C16/32 ,  G11C16/12

Abstract: Programming methods include programming first and second data in first and second memory cells, reading the first data from the first memory cell by applying a read voltage to an access line connected to the first and second memory cells while the first memory cell is electrically connected to a data line and while the second memory cell is electrically disconnected from the data line, reading the second data from the second memory cell by electrically disconnecting the first memory cell from the data line and electrically connecting the second memory cell to the data line while the read voltage remains applied to the access line, and programming the read first data and the read second data in a single memory cell connected to a different access line.

公开(公告)号：US20190027222A1

公开(公告)日：2019-01-24

申请号：US16141717

申请日：2018-09-25

Applicant: Micron Technology, Inc.

Inventor： Toru Tanzawa

IPC: G11C16/26 ,  G11C16/34 ,  G11C16/04 ,  G11C16/12 ,  G11C16/10 ,  G11C7/00

CPC classification number: G11C16/26 ,  G11C7/00 ,  G11C16/0408 ,  G11C16/10 ,  G11C16/12 ,  G11C16/3459

Abstract: Embodiments are provided that include a memory device having a memory array including a plurality of access lines and data lines. The memory device further includes a circuit coupled to the plurality of access lines and configured to provide consecutive pulses to a selected one of the plurality of access lines. Each pulse of the consecutive pulses includes a first voltage and a second voltage. The first voltage is greater in magnitude than the second voltage, and the first voltage is applied for a shorter duration than the second voltage.

公开(公告)号：US10163928B2

公开(公告)日：2018-12-25

申请号：US15693229

申请日：2017-08-31

Applicant: Micron Technology, Inc.

Inventor： Toru Tanzawa

IPC: H01L27/115 ,  H01L27/11582 ,  H01L27/11556 ,  H01L23/528 ,  H01L27/11524 ,  H01L27/1157 ,  G11C16/08 ,  G11C16/10 ,  G11C5/06

Abstract: Some embodiments include apparatuses and methods having a conductive line, a memory cell string including memory cells located in different levels the apparatus, and a select circuit including a select transistor and a coupling component coupled between the conductive line and the memory cell string. Other embodiments including additional apparatuses and methods are described.

公开(公告)号：US20180322930A1

公开(公告)日：2018-11-08

申请号：US16035933

申请日：2018-07-16

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Koji Sakui ,  Mark Hawes ,  Toru Tanzawa ,  Jeremy Binfet

IPC: G11C16/26 ,  G11C16/04 ,  G11C16/20 ,  G11C16/34 ,  H01L27/115 ,  G11C16/08 ,  G11C7/04 ,  G11C16/32 ,  G11C16/14 ,  G11C16/30

CPC classification number: G11C16/26 ,  G11C7/04 ,  G11C16/0483 ,  G11C16/08 ,  G11C16/14 ,  G11C16/20 ,  G11C16/30 ,  G11C16/32 ,  G11C16/3418 ,  G11C16/3427 ,  H01L27/115 ,  H01L27/11519 ,  H01L27/11529 ,  H01L27/11556

Abstract: Apparatus and methods of operating such apparatus include establishing a negative potential in a body of a memory cell in response to a timer, or during an access operation of another memory cell.