公开(公告)号：US09570126B2

公开(公告)日：2017-02-14

申请号：US15138424

申请日：2016-04-26

Applicant: Rambus Inc.

Inventor： James E. Harris ,  Thomas Vogelsang ,  Frederick A. Ware ,  Ian P. Shaeffer

IPC: G11C7/00 ,  G11C7/12 ,  G11C5/02 ,  G11C7/10 ,  G11C11/4076 ,  G11C11/408 ,  G11C11/4091 ,  G11C7/06 ,  G11C7/08 ,  G11C7/22

CPC classification number: G11C7/1039 ,  G11C5/025 ,  G11C7/06 ,  G11C7/065 ,  G11C7/08 ,  G11C7/12 ,  G11C7/222 ,  G11C8/08 ,  G11C8/10 ,  G11C11/4076 ,  G11C11/4087 ,  G11C11/4091

Abstract: Row activation operations within a memory component are carried out with respect to subrows instead of complete storage rows to reduce power consumption. Further, instead of activating subrows in response to row commands, subrow activation operations are deferred until receipt of column commands that specify the column operation to be performed and the subrow to be activated.

Abstract translation: 存储器组件内的行激活操作相对于子行执行，而不是完整的存储行，以减少功耗。 此外，代替激活响应于行命令的子代码，延迟激活操作被延迟，直到接收到指定要执行的列操作的列命令和被激活的子代。

公开(公告)号：US09563228B2

公开(公告)日：2017-02-07

申请号：US14954940

申请日：2015-11-30

Applicant: Rambus Inc.

Inventor： Jared L. Zerbe ,  Ian P. Shaeffer ,  John Eble

IPC: G06F1/04 ,  G06F1/10 ,  G06F13/16 ,  G11C7/22 ,  G06F1/06 ,  G06F1/08 ,  H04L7/033 ,  G11C7/04

CPC classification number: G06F13/1689 ,  G06F1/04 ,  G06F1/06 ,  G06F1/08 ,  G06F1/10 ,  G06F13/161 ,  G06F13/1657 ,  G11C7/04 ,  G11C7/222 ,  H04L7/033

Abstract: A memory controller includes a clock generator to generate a first clock signal and a timing circuit to generate a second clock signal from the first clock signal. The second clock signal times communications with any of a plurality of memory devices in respective ranks, including a first memory device in a first rank and a second memory device in a second rank. The timing circuit is configured to adjust a phase of the first clock signal, when the memory controller is communicating with the second memory device, based on calibration data associated with the second memory device and timing adjustment data associated with feedback from at least the first memory device.

Abstract translation: 存储器控制器包括时钟发生器，用于产生第一时钟信号和定时电路，以从第一时钟信号产生第二时钟信号。 第二时钟信号与相应等级中的多个存储器件中的任何一个存储器件进行通信，包括第一等级中的第一存储器件和第二等级的第二存储器件。 定时电路被配置为基于与第二存储器设备相关联的校准数据和与来自至少第一存储器的反馈相关联的定时调整数据来调整存储器控制器与第二存储器件通信时的第一时钟信号的相位 设备。

公开(公告)号：US09337835B2

公开(公告)日：2016-05-10

申请号：US14857794

申请日：2015-09-17

Applicant: Rambus Inc.

Inventor： Kyung Suk Oh ,  Ian P. Shaeffer

IPC: H03K17/16 ,  H03K19/00 ,  G06F13/40 ,  G11C11/4093 ,  H03K19/0175 ,  G11C11/401 ,  G11C11/419 ,  G11C16/26 ,  G11C11/41 ,  G11C11/4063 ,  G11C11/413 ,  G11C11/417 ,  G11C16/06 ,  G11C16/32

CPC classification number: H03K19/0005 ,  G06F3/0605 ,  G06F3/0659 ,  G06F3/0685 ,  G06F13/4086 ,  G11C11/401 ,  G11C11/4063 ,  G11C11/4093 ,  G11C11/41 ,  G11C11/413 ,  G11C11/417 ,  G11C11/419 ,  G11C16/06 ,  G11C16/26 ,  G11C16/32 ,  H03K19/017545

Abstract: An IC die transmits command signals, address signals and data signals to a flash memory device at respective times via a time-multiplexed external signaling line, the data signals representing data to be stored within an array of non-volatile storage elements of the flash memory device. The IC die additionally transmits a control signal to the flash memory device via one or more external control signal lines, the control signal directing the flash memory device to switchably couple an on-die termination element to the time-multiplexed signaling line.

Abstract translation: IC芯片经由时间复用的外部信号线在各自的时间将命令信号，地址信号和数据信号发送到闪速存储器件，数据信号表示要存储在闪速存储器的非易失性存储元件阵列内的数据 设备。 IC芯片还经由一个或多个外部控制信号线将控制信号发送到闪速存储器件，该控制信号指示闪速存储器件可切换地将片上端接元件耦合到时分多路信号线。

公开(公告)号：US20160116938A1

公开(公告)日：2016-04-28

申请号：US14954940

申请日：2015-11-30

Applicant: Rambus Inc.

Inventor： Jared L. Zerbe ,  Ian P. Shaeffer ,  John Eble

IPC: G06F1/10 ,  G11C7/22

CPC classification number: G06F13/1689 ,  G06F1/04 ,  G06F1/06 ,  G06F1/08 ,  G06F1/10 ,  G06F13/161 ,  G06F13/1657 ,  G11C7/04 ,  G11C7/222 ,  H04L7/033

Abstract: A memory controller includes a clock generator to generate a first clock signal and a timing circuit to generate a second clock signal from the first clock signal. The second clock signal times communications with any of a plurality of memory devices in respective ranks, including a first memory device in a first rank and a second memory device in a second rank. The timing circuit is configured to adjust a phase of the first clock signal, when the memory controller is communicating with the second memory device, based on calibration data associated with the second memory device and timing adjustment data associated with feedback from at least the first memory device.

Abstract translation: 存储器控制器包括时钟发生器，用于产生第一时钟信号和定时电路，以从第一时钟信号产生第二时钟信号。 第二时钟信号与相应等级中的多个存储器件中的任何一个存储器件进行通信，包括第一等级中的第一存储器件和第二等级的第二存储器件。 定时电路被配置为基于与第二存储器设备相关联的校准数据和与来自至少第一存储器的反馈相关联的定时调整数据来调整存储器控制器与第二存储器件通信时的第一时钟信号的相位 设备。

公开(公告)号：US09306565B2

公开(公告)日：2016-04-05

申请号：US14711538

申请日：2015-05-13

Applicant: Rambus Inc.

Inventor： Kyung Suk Oh ,  Ian P. Shaeffer

IPC: H03K17/16 ,  H03K19/00 ,  G06F13/40 ,  G11C11/4093 ,  H03K19/0175 ,  G11C11/401 ,  G11C11/419 ,  G11C16/26 ,  G11C11/41 ,  G11C11/4063 ,  G11C11/413 ,  G11C11/417 ,  G11C16/06 ,  G11C16/32

CPC classification number: H03K19/0005 ,  G06F3/0605 ,  G06F3/0659 ,  G06F3/0685 ,  G06F13/4086 ,  G11C11/401 ,  G11C11/4063 ,  G11C11/4093 ,  G11C11/41 ,  G11C11/413 ,  G11C11/417 ,  G11C11/419 ,  G11C16/06 ,  G11C16/26 ,  G11C16/32 ,  H03K19/017545

Abstract: A non-volatile memory device determines, based at least partly on a first multi-bit device address received via a signaling interface and an incoming chip-select signal, whether the device is to participate in a memory access transaction by receiving or outputting data via an I/O node of the signaling interface. Based at least in part on that determination, on-die termination circuitry within the non-volatile memory device switchably couples or decouples a termination resistance between the I/O node and a supply voltage node during a data transmission phase of the memory access transaction.

Abstract translation: 至少部分地基于经由信令接口和输入芯片选择信号接收到的第一多位设备地址来确定设备是否通过接收或输出数据来参与存储器访问事务，非易失性存储器设备 信令接口的I / O节点。 至少部分地基于该确定，在存储器访问事务的数据传输阶段期间，非易失性存储器件内的片上终端电路可切换地将I / O节点和电源电压节点之间的终端电阻耦合或去耦。

公开(公告)号：US20150249451A1

公开(公告)日：2015-09-03

申请号：US14712763

申请日：2015-05-14

Applicant: Rambus Inc.

Inventor： Kyung Suk Oh ,  Ian P. Shaeffer

IPC: H03K19/00 ,  G11C11/4063 ,  G11C11/413 ,  H03K19/0175

CPC classification number: H03K19/0005 ,  G06F3/0605 ,  G06F3/0659 ,  G06F3/0685 ,  G06F13/4086 ,  G11C11/401 ,  G11C11/4063 ,  G11C11/4093 ,  G11C11/41 ,  G11C11/413 ,  G11C11/417 ,  G11C11/419 ,  G11C16/06 ,  G11C16/26 ,  G11C16/32 ,  H03K19/017545

Abstract: An identifier value stored within a programmable register of a memory device is compared with a selector address received, together with a memory access command, via a signaling interface having at least one I/O node coupled to a bidirectional signaling line. On-die termination circuitry is transitioned between first and second states or maintained in one or the other of the first and second states based, at least in part, on whether the selector address matches the identifier value, with transition to the first state including switchably coupling a first termination resistance between the I/O node and a supply voltage line.

Abstract translation: 存储在存储器件的可编程寄存器中的标识符值与经由具有耦合到双向信令线的至少一个I / O节点的信令接口的存储器访问命令一起被接收的选择器地址进行比较。 至少部分地，至少部分地基于选择器地址是否与标识符值匹配，在第一状态和第二状态之间转换到第一状态或第二状态之间的转换到包括可切换的状态 耦合I / O节点和电源电压线之间的第一终端电阻。

公开(公告)号：US20130307584A1

公开(公告)日：2013-11-21

申请号：US13952393

申请日：2013-07-26

Applicant: Rambus Inc.

Inventor： Kyung Suk Oh ,  Ian P. Shaeffer

IPC: H03K19/0175

CPC classification number: H03K19/0005 ,  G06F3/0605 ,  G06F3/0659 ,  G06F3/0685 ,  G06F13/4086 ,  G11C11/401 ,  G11C11/4063 ,  G11C11/4093 ,  G11C11/41 ,  G11C11/413 ,  G11C11/417 ,  G11C11/419 ,  G11C16/06 ,  G11C16/26 ,  G11C16/32 ,  H03K19/017545

Abstract: An integrated circuit memory device stores a plurality of digital values that specify respective termination impedances. The memory device switchably couples respective sets of load elements to a data input/output (I/O) to apply the termination impedances specified by the digital values, including, applying a first termination impedance to the data I/O during an idle state of the memory device, applying a first one of two non-equal termination impedances to the data I/O while the memory device receives write data in a memory write operation and applying a second one of the two non-equal termination impedances to the data I/O while another memory device receives write data in a memory write operation. When outputting read data via the data I/O in a memory read operation, the memory device switchably couples to the data I/O at least a portion of the load elements included in the sets of load elements.

Abstract translation: 集成电路存储器件存储指定相应终端阻抗的多个数字值。 存储器件可将各组负载元件可切换地耦合到数据输入/输出（I / O），以施加由数字值指定的终端阻抗，包括在空闲状态期间向数据I / O施加第一终端阻抗 所述存储器件在所述存储器件在存储器写入操作中接收到写入数据并将所述两个不相等的终端阻抗中的第二个施加到所述数据I上时，将两个不相等的终端阻抗中的第一个施加到所述数据I / O / O，而另一个存储器件在存储器写入操作中接收写入数据。 当在存储器读取操作中经由数据I / O输出读取数据时，存储器件可切换地耦合到包含在负载元件组中的负载元件的至少一部分的数据I / O。