公开(公告)号：US09324411B2

公开(公告)日：2016-04-26

申请号：US14797057

申请日：2015-07-10

Applicant: Rambus Inc.

Inventor： Scott C. Best ,  Ming Li

IPC: G11C8/00 ,  G11C11/4096 ,  G11C11/4093 ,  G11C5/02 ,  G11C5/04 ,  H01L25/10 ,  H01L25/18 ,  H01L25/065

CPC classification number: G11C11/4093 ,  G11C5/02 ,  G11C5/025 ,  G11C5/04 ,  G11C11/4096 ,  H01L23/481 ,  H01L24/73 ,  H01L25/0652 ,  H01L25/0657 ,  H01L25/105 ,  H01L25/18 ,  H01L2224/0401 ,  H01L2224/16225 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48225 ,  H01L2224/48227 ,  H01L2224/73265 ,  H01L2225/0651 ,  H01L2225/0652 ,  H01L2225/06541 ,  H01L2225/06558 ,  H01L2225/06562 ,  H01L2225/1023 ,  H01L2225/1058 ,  H01L2924/00011 ,  H01L2924/00014 ,  H01L2924/01019 ,  H01L2924/01055 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/15321 ,  H01L2924/15331 ,  H01L2924/3011 ,  H01L2924/00012 ,  H01L2924/00

Abstract: A memory is disclosed that includes a logic die having first and second memory interface circuits. A first memory die is stacked with the logic die, and includes first and second memory arrays. The first memory array couples to the first memory interface circuit. The second memory array couples to the second interface circuit. A second memory die is stacked with the logic die and the first memory die. The second memory die includes third and fourth memory arrays. The third memory array couples to the first memory interface circuit. The fourth memory array couples to the second memory interface circuit. Accesses to the first and third memory arrays are carried out independently from accesses to the second and fourth memory arrays.

公开(公告)号：US09256376B2

公开(公告)日：2016-02-09

申请号：US14452373

申请日：2014-08-05

Applicant: Rambus Inc.

Inventor： Ely Tsern ,  Thomas Vogelsang ,  Craig Hampel ,  Scott C. Best

IPC: G11C7/00 ,  G06F3/06 ,  G11C11/4074 ,  G06F1/26 ,  G11C5/14

CPC classification number: G06F3/0625 ,  G06F1/266 ,  G06F3/0634 ,  G06F3/0673 ,  G11C5/147 ,  G11C11/4074 ,  G11C2207/2227

Abstract: A memory system supports high-performance and low-power modes. The memory system includes a memory core and a core interface. The memory core employs core supply voltages that remain the same in both modes. Supply voltages and signaling rates for the core interface may be scaled down to save power. Level shifters between the memory core and core interface level shift signals as needed to accommodate the signaling voltages used by the core interface in the different modes.

Abstract translation: 内存系统支持高性能和低功耗模式。 存储器系统包括存储器核和核心接口。 存储器内核采用在两种模式下保持相同的核心电源电压。 核心接口的电源电压和信号速率可以缩小以节省功耗。 存储器核心和核心接口电平之间的电平移位器根据需要移位信号以适应不同模式下核心接口所使用的信令电压。

公开(公告)号：US09183920B2

公开(公告)日：2015-11-10

申请号：US14578078

申请日：2014-12-19

Applicant: RAMBUS INC.

Inventor： Frederick A. Ware ,  Suresh Rajan ,  Scott C. Best

IPC: G06F3/00 ,  G11C11/4093 ,  G11C5/04 ,  G11C11/408 ,  G06F12/06 ,  G06F13/16 ,  G11C7/10

CPC classification number: G11C11/4082 ,  G06F12/06 ,  G06F13/1673 ,  G06F13/1684 ,  G11C5/04 ,  G11C7/1051 ,  G11C7/1078 ,  G11C7/22 ,  G11C11/4076 ,  G11C11/4093

Abstract: The embodiments described herein describe technologies for using the memory modules in different modes of operation, such as in a standard multi-drop mode or as in a dynamic point-to-point (DPP) mode (also referred to herein as an enhanced mode). The memory modules can also be inserted in the sockets of the memory system in different configurations.

Abstract translation: 本文描述的实施例描述了在不同操作模式下使用存储器模块的技术，例如在标准多点模式或动态点对点（DPP）模式（此处也称为增强模式）中， 。 内存模块也可以以不同的配置插入存储系统的插座。

公开(公告)号：US20150248936A1

公开(公告)日：2015-09-03

申请号：US14621171

申请日：2015-02-12

Applicant: Rambus Inc.

Inventor： Scott C. Best ,  Brent Steven Haukness

IPC: G11C15/04

CPC classification number: G11C15/046 ,  G11C13/0002

Abstract: A ternary content-addressable memory (TCAM) array of cells features reduced area and improved matching functionality. 1T-3R and 2T-3R embodiments are disclosed as illustrative. A row or block of TCAM memory cells may include a serial string interconnecting the cells so as to provide reduced power consumption during matching operations. In other aspects, Pre-charge/Discharge logic configurations are described utilizing complementary resistive ram (cRRAM) storage for input data to form improved programmable logic circuits.

Abstract translation: 三元内容可寻址存储器（TCAM）单元阵列具有减少的面积和改进的匹配功能。 公开了1T-3R和2T-3R实施例作为说明。 TCAM存储器单元的行或块可以包括互连单元的串行串，以便在匹配操作期间提供降低的功耗。 在其他方面，使用用于输入数据的互补电阻RAM（cRRAM）存储来描述预充电/放电逻辑配置，以形成改进的可编程逻辑电路。

公开(公告)号：US09047942B2

公开(公告)日：2015-06-02

申请号：US14458212

申请日：2014-08-12

Applicant: Rambus Inc.

Inventor： Scott C. Best

IPC: G11C7/00 ,  G11C14/00 ,  G06F12/06 ,  G06F13/16 ,  G06F12/02

CPC classification number: G11C14/0018 ,  G06F12/0246 ,  G06F12/0638 ,  G06F13/1694

Abstract: Non-transitory computer-readable media having information embodied therein that includes a description of an integrated circuit device. The information includes descriptions of a volatile storage die having a first addressable range of storage cells and a non-volatile storage die. The description of the non-volatile storage die having a second addressable range of storage cells that defines an overlapping region with the first addressable range of storage cells. The information also includes a description of an interface circuit coupled to the volatile and non-volatile storage die to selectively transfer data stored in the overlapping region of storage cells between the die.

Abstract translation: 具有体现在其中的信息的非瞬时计算机可读介质包括集成电路设备的描述。 该信息包括具有第一可寻址范围的存储单元和非易失性存储管芯的易失性存储管芯的描述。 具有第二可寻址范围的存储单元的非易失性存储管芯的描述，其定义与存储单元的第一可寻址范围重叠的区域。 该信息还包括耦合到易失性和非易失性存储管芯的接口电路的描述，以选择性地传输存储在管芯之间的存储单元的重叠区域中的数据。

公开(公告)号：US20150082119A1

公开(公告)日：2015-03-19

申请号：US14475619

申请日：2014-09-03

Applicant: Rambus Inc.

Inventor： Frederick A. Ware ,  Scott C. Best

IPC: H03M13/15 ,  G06F11/10 ,  H03M13/00

CPC classification number: G06F11/1048 ,  H03M13/1525 ,  H03M13/19 ,  H03M13/617

Abstract: A memory system includes a memory module that supports error detection and correction (EDC) in a manner that relieves a memory controller or processor of some or all of the computational burden associated with EDC. individual EDC components perform EDC functions on subsets of the data, and share data between themselves using relatively short, fast interconnections.

Abstract translation: 存储器系统包括以能够缓解存储器控制器或处理器与EDC相关联的一些或全部计算负担的方式支持错误检测和校正（EDC）的存储器模块。 单独的EDC组件在数据子集上执行EDC功能，并使用相对较短，快速的互连在其间共享数据。

公开(公告)号：US20140351500A1

公开(公告)日：2014-11-27

申请号：US14458212

申请日：2014-08-12

Applicant: Rambus Inc.

Inventor： Scott C. Best

IPC: G11C14/00 ,  G06F12/02

CPC classification number: G11C14/0018 ,  G06F12/0246 ,  G06F12/0638 ,  G06F13/1694

Abstract: Non-transitory computer-readable media having information embodied therein that includes a description of an integrated circuit device. The information includes descriptions of a volatile storage die having a first addressable range of storage cells and a non-volatile storage die. The description of the non-volatile storage die having a second addressable range of storage cells that defines an overlapping region with the first addressable range of storage cells. The information also includes a description of an interface circuit coupled to the volatile and non-volatile storage die to selectively transfer data stored in the overlapping region of storage cells between the die.

Abstract translation: 具有体现在其中的信息的非瞬时计算机可读介质包括集成电路设备的描述。 该信息包括具有第一可寻址范围的存储单元和非易失性存储管芯的易失性存储管芯的描述。 具有第二可寻址范围的存储单元的非易失性存储管芯的描述，其定义与存储单元的第一可寻址范围重叠的区域。 该信息还包括耦合到易失性和非易失性存储管芯的接口电路的描述，以选择性地传输存储在管芯之间的存储单元的重叠区域中的数据。

公开(公告)号：US08837236B2

公开(公告)日：2014-09-16

申请号：US13867963

申请日：2013-04-22

Applicant: Rambus Inc.

Inventor： Scott C. Best

IPC: G11C7/00 ,  G11C14/00 ,  G06F12/06 ,  G06F13/16

CPC classification number: G11C14/0018 ,  G06F12/0246 ,  G06F12/0638 ,  G06F13/1694

Abstract: A composite, hybrid memory device including a first storage die having an array of volatile storage cells and a second storage die having an array of non-volatile storage cells disposed within an integrated circuit package. The hybrid memory device includes a shared interface circuit to receive memory access commands directed to the first storage die and the second storage die and to convey read and write data between an external data path and the first and second storage dice.

Abstract translation: 一种复合混合存储器件，包括具有易失性存储单元阵列的第一存储管芯和具有设置在集成电路封装内的非易失性存储单元阵列的第二存储管芯。 混合存储装置包括共享接口电路，用于接收指向第一存储管芯和第二存储管芯的存储器访问命令，并且在外部数据通路与第一和第二存储管芯之间传送读取和写入数据。

公开(公告)号：US20140233333A1

公开(公告)日：2014-08-21

申请号：US14182389

申请日：2014-02-18

Applicant: Rambus Inc.

Inventor： Scott C. Best ,  Richard E. Warmke ,  David B. Roberts ,  Frank Lambrecht

IPC: G11C7/22 ,  G11C7/10

CPC classification number: G11C11/4076 ,  G06F1/10 ,  G11C7/04 ,  G11C7/10 ,  G11C7/1087 ,  G11C7/222 ,  G11C11/4091 ,  G11C2207/107 ,  H03L7/07 ,  H03L7/0814 ,  H04L7/0337

Abstract: A memory controller receives data and phase-providing signals from a memory device. The phase-providing signal is not a clock signal, but is used by the memory controller to phase align a local data-sampling signal with the incoming data. The memory controller samples the data signal with the data-sampling signal. The memory controller can perform maintenance operations to update the phase relationship between the phase-providing and data-sampling signals.

Abstract translation: 存储器控制器从存储器件接收数据和相位提供信号。 相位提供信号不是时钟信号，而是被存储器控制器用来将本地数据采样信号与输入数据进行相位调整。 存储器控制器用数据采样信号对数据信号进行采样。 存储器控制器可以执行维护操作以更新相位提供和数据采样信号之间的相位关系。

公开(公告)号：US20130308383A1

公开(公告)日：2013-11-21

申请号：US13867963

申请日：2013-04-22

Applicant: Rambus, Inc.

Inventor： Scott C. Best

IPC: G11C14/00

CPC classification number: G11C14/0018 ,  G06F12/0246 ,  G06F12/0638 ,  G06F13/1694

Abstract: A composite, hybrid memory device including a first storage die having an array of volatile storage cells and a second storage die having an array of non-volatile storage cells disposed within an integrated circuit package. The hybrid memory device includes a shared interface circuit to receive memory access commands directed to the first storage die and the second storage die and to convey read and write data between an external data path and the first and second storage dice.

Abstract translation: 一种复合混合存储器件，包括具有易失性存储单元阵列的第一存储管芯和具有设置在集成电路封装内的非易失性存储单元阵列的第二存储管芯。 混合存储装置包括共享接口电路，用于接收指向第一存储管芯和第二存储管芯的存储器访问命令，并且在外部数据通路与第一和第二存储管芯之间传送读取和写入数据。