公开(公告)号：US12079559B2

公开(公告)日：2024-09-03

申请号：US18362889

申请日：2023-07-31

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

Inventor： Shih-Wei Peng ,  Guo-Huei Wu ,  Wei-Cheng Lin ,  Hui-Zhong Zhuang ,  Jiann-Tyng Tzeng

IPC: G06F30/392 ,  G03F1/36 ,  G03F7/00 ,  G06F30/398

CPC classification number: G06F30/392 ,  G03F1/36 ,  G03F7/70441 ,  G06F30/398

Abstract: A method of generating an IC layout diagram includes overlapping a channel region of an upper transistor of a complementary field-effect transistor (CFET) in an IC layout with a gate region of the CFET, thereby defining a channel overlap region, positioning an isolation region in the IC layout, the isolation region including an entirety of the channel overlap region, intersecting the isolation region with a conductive region, and generating an IC layout diagram based on the IC layout.

公开(公告)号：US12033998B2

公开(公告)日：2024-07-09

申请号：US18363230

申请日：2023-08-01

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

Inventor： Kuang-Ching Chang ,  Jung-Chan Yang ,  Hui-Zhong Zhuang ,  Chih-Liang Chen ,  Kuo-Nan Yang

IPC: H01L27/02 ,  G06F1/3287

CPC classification number: H01L27/0207 ,  G06F1/3287

Abstract: An integrated circuit includes a gated circuit configured to operate on at least a first or a second voltage, a header circuit coupled to the gated circuit, a first and second power rail on a back-side of a wafer, and a third power rail on a front-side of the wafer. The header circuit is configured to supply the first voltage to the gated circuit by the first power rail. The first power rail includes a first portion, a second portion and a third portion, the third portion being between the first portion and the second portion. The second power rail is configured to supply the second voltage to the gated circuit, and is between the first portion and the second portion. The third power rail includes a first set of conductors. Each of the first set of conductors being configured to supply a third voltage to the header circuit.

公开(公告)号：US11894383B2

公开(公告)日：2024-02-06

申请号：US17829330

申请日：2022-05-31

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.

Inventor： Pochun Wang ,  Guo-Huei Wu ,  Hui-Zhong Zhuang ,  Chih-Liang Chen ,  Li-Chun Tien

IPC: H01L27/12 ,  H01L21/84 ,  H01L23/522 ,  H01L23/528 ,  B82Y10/00 ,  H01L21/822 ,  H01L21/8238 ,  H01L29/66 ,  H01L29/775 ,  H01L21/768 ,  H01L27/02 ,  H01L27/06 ,  H01L27/092 ,  H01L29/423 ,  H01L29/786 ,  H01L21/74 ,  H01L27/088 ,  H01L21/8234

CPC classification number: H01L27/1211 ,  H01L21/845 ,  H01L23/528 ,  H01L23/5226

Abstract: A semiconductor structure includes a first transistor, a second transistor, a first dummy source/drain, a third transistor, a fourth transistor, and a second dummy source/drain. The first transistor and a second transistor adjacent to the first transistor are at a first elevation. The first dummy source/drain is disposed at the first elevation. The third transistor and a fourth transistor adjacent to the third transistor, are at a second elevation different from the first elevation. The second dummy source/drain is disposed at the second elevation. The second transistor is vertically aligned with the third transistor. The first dummy source/drain is vertically aligned with a source/drain of the fourth transistor. The second dummy source/drain is vertically aligned with a source/drain of the first transistor. The gate structure between the second dummy source/drain and a source/drain of the third transistor is absent. A method for manufacturing a semiconductor structure is also provided.

公开(公告)号：US11862637B2

公开(公告)日：2024-01-02

申请号：US16879166

申请日：2020-05-20

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Shao-Lun Chien ,  Ting-Wei Chiang ,  Hui-Zhong Zhuang ,  Pin-Dai Sue

IPC: H01L27/092 ,  H01L27/088 ,  H01L21/8234 ,  H01L23/528 ,  H01L23/522 ,  H01L21/765 ,  H01L21/8238

CPC classification number: H01L27/0924 ,  H01L21/765 ,  H01L21/823412 ,  H01L21/823821 ,  H01L21/823828 ,  H01L21/823871 ,  H01L21/823878 ,  H01L23/5226 ,  H01L23/5286 ,  H01L27/088 ,  H01L27/092 ,  H01L27/0922

Abstract: An integrated circuit device includes a first power rail, a first active area extending in a first direction, and a plurality of gates contacting the first active area and extending in a second direction perpendicular to the first direction. A first transistor includes the first active area and a first one of the gates. The first transistor has a first threshold voltage (VT). A second transistor includes the first active area and a second one of the gates. The second transistor has a second VT different than the first VT. A tie-off transistor is positioned between the first transistor and the second transistor, and includes the first active area and a third one of the gates, wherein the third gate is connected to the first power rail.

公开(公告)号：US11855069B2

公开(公告)日：2023-12-26

申请号：US17371631

申请日：2021-07-09

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

Inventor： Jian-Sing Li ,  Chi-Yu Lu ,  Hui-Zhong Zhuang ,  Chih-Liang Chen

IPC: H01L21/8238 ,  H01L27/02 ,  H01L27/092 ,  G06F30/392 ,  H01L29/423

CPC classification number: H01L27/0207 ,  G06F30/392 ,  H01L21/82385 ,  H01L27/092 ,  H01L29/42376

Abstract: A method of fabricating an integrated circuit. The method includes generating two first-type active zones and two second-type active zones, and generating a gate-strip intersecting the two first-type active zones and the two second-type active zones. The method further includes patterning one or more poly cuts intersecting the gate-strip based on a determination of a difference between the poly extension effect of a p-type transistor and the poly extension effect of an n-type transistor.

公开(公告)号：US11854940B2

公开(公告)日：2023-12-26

申请号：US17231527

申请日：2021-04-15

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

Inventor： Chih-Yu Lai ,  Chih-Liang Chen ,  Chi-Yu Lu ,  Shang-Syuan Ciou ,  Hui-Zhong Zhuang ,  Ching-Wei Tsai ,  Shang-Wen Chang

IPC: H01L23/48 ,  H01L21/768

CPC classification number: H01L23/481 ,  H01L21/76897 ,  H01L21/76898

Abstract: A semiconductor device includes a substrate and a first transistor on a first side of the substrate. The semiconductor device further includes a first electrode contacting a first region of the first transistor. The semiconductor device further includes a spacer extending along a sidewall of the first transistor. The semiconductor device further includes a self-aligned interconnect structure (SIS) separated from at least a portion of the first electrode by the spacer, wherein the SIS extends through the substrate. The semiconductor device further includes a second electrode contacting a surface of the first electrode farthest from the substrate, wherein the second electrode directly contacts the SIS.

公开(公告)号：US11842137B2

公开(公告)日：2023-12-12

申请号：US17406699

申请日：2021-08-19

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

Inventor： Shih-Wei Peng ,  Chih-Liang Chen ,  Charles Chew-Yuen Young ,  Hui-Zhong Zhuang ,  Jiann-Tyng Tzeng ,  Shun Li Chen ,  Wei-Cheng Lin

IPC: G06F30/00 ,  G06F30/398 ,  H01L27/02 ,  H01L27/118 ,  G06F30/39 ,  G06F30/394

CPC classification number: G06F30/398 ,  G06F30/39 ,  G06F30/394 ,  H01L27/0207 ,  H01L27/11807 ,  H01L2027/11875

Abstract: An integrated circuit includes a set of gates, a first, second and third conductive structure, and a first, second and third via. The set of gates includes a first, second and third gate. The first, second and third conductive structure extend in the first direction and are located on a second level. The first via couples the first conductive structure and the first gate. The second via couples the second conductive structure and the second gate. The third via couples the third conductive structure and the third gate. The first, second and third via are in a right angle configuration. The first and second gate are separated from each other by a first pitch. The first and third gate are separated from each other by a removed gate portion. The first and second conductive structure are separated from each other in the first direction.

公开(公告)号：US11783109B2

公开(公告)日：2023-10-10

申请号：US17395148

申请日：2021-08-05

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

Inventor： Shih-Wei Peng ,  Guo-Huei Wu ,  Wei-Cheng Lin ,  Hui-Zhong Zhuang ,  Jiann-Tyng Tzeng

IPC: G06F30/392 ,  G03F7/20 ,  G03F1/36 ,  G06F30/398 ,  G03F7/00

CPC classification number: G06F30/392 ,  G03F1/36 ,  G03F7/70441 ,  G06F30/398

Abstract: A method of forming an IC device includes creating a recess by removing at least a portion of a channel of a first transistor and a portion of a gate electrode, the gate electrode being common to the first transistor and an underlying second transistor. The method includes filling the recess with a dielectric material to form an isolation layer, and constructing a slot via overlying the isolation layer.

公开(公告)号：US11768989B2

公开(公告)日：2023-09-26

申请号：US17558157

申请日：2021-12-21

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

Inventor： Chi-Yu Lu ,  Hui-Zhong Zhuang ,  Pin-Dai Sue ,  Yi-Hsin Ko ,  Li-Chun Tien

IPC: G06F30/392 ,  G06F30/398

CPC classification number: G06F30/392 ,  G06F30/398

Abstract: A method of designing a semiconductor device including the operations of analyzing a vertical abutment between a first standard cell block and a second cell block and, if a mismatch is identified between the first standard cell block and the second cell block initiating the selection of a first modified cell block that reduces the mismatch and a spacing between the first modified cell block and the second cell block, the first modified cell block comprising a first abutment region having a continuous active region arranged along a first axis parallel to an edge of the vertical abutment, and replacing the first standard cell block with the first modified cell block to obtain a first modified layout design and devices manufactured according to the method.

公开(公告)号：US11756999B2

公开(公告)日：2023-09-12

申请号：US17205670

申请日：2021-03-18

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

Inventor： Jung-Chan Yang ,  Hui-Zhong Zhuang ,  Lee-Chung Lu ,  Ting-Wei Chiang ,  Li-Chun Tien

IPC: H01L29/06 ,  H01L27/092 ,  H01L27/02 ,  H01L21/033 ,  H01L29/66 ,  H01L29/78 ,  H01L21/8238 ,  G06F30/392

CPC classification number: H01L29/0696 ,  G06F30/392 ,  H01L21/0337 ,  H01L21/823821 ,  H01L27/0207 ,  H01L27/0924 ,  H01L29/6681 ,  H01L29/66545 ,  H01L29/7851

Abstract: In at least one cell region, a semiconductor device includes fin patterns and at least one overlying gate structure. The fin patterns (dummy and active) are substantially parallel to a first direction. Each gate structure is substantially parallel to a second direction (which is substantially perpendicular to the first direction). First and second active fin patterns have corresponding first and second conductivity types. Each cell region, relative to the second direction, includes: a first active region which includes a sequence of three or more consecutive first active fin patterns located in a central portion of the cell region; a second active region which includes one or more second active fin patterns located between the first active region and a first edge of the cell region; and a third active region which includes one or more second active fin patterns located between the first active region and a second edge of the cell region.