公开(公告)号：US20050093020A1

公开(公告)日：2005-05-05

申请号：US10983610

申请日：2004-11-09

申请人： Akira Inoue ,  Takeshi Takagi ,  Yoshihiro Hara ,  Minoru Kubo

发明人： Akira Inoue ,  Takeshi Takagi ,  Yoshihiro Hara ,  Minoru Kubo

IPC分类号： H01L21/02 ,  H01L21/314 ,  H01L21/316 ,  H01L21/77 ,  H01L21/8238 ,  H01L21/8242 ,  H01L21/8246 ,  H01L21/84 ,  H01L27/092 ,  H01L27/115 ,  H01L27/12 ,  H01L29/10 ,  H01L29/78 ,  H01L29/786 ,  H01L29/80 ,  H01L31/0392

CPC分类号： H01L29/802 ,  H01L21/823807 ,  H01L21/84 ,  H01L27/092 ,  H01L27/10873 ,  H01L27/11502 ,  H01L27/11507 ,  H01L27/1203 ,  H01L27/1214 ,  H01L27/1222 ,  H01L28/55 ,  H01L29/1054 ,  H01L29/783 ,  H01L29/78687

摘要： A silicon oxide film 102, a Pt film 103x, a Ti film 104x and a PZT film 105x are deposited in this order over a Si substrate 101. The Si substrate 101 is placed in a chamber 106 so that the PZT film 105x is irradiated with an EHF wave 108. The irradiation with the EHF wave locally heats a dielectric film such as the PZT film. As a result, it is possible to improve, for example, the leakage property of the dielectric film without adversely affecting a device formed on the Si substrate 101.

摘要翻译： 依次沉积硅衬底101上的氧化硅膜102，Pt膜103x，Ti膜104x和PZT膜105x。 将Si衬底101放置在室106中，使得PZT膜105x被EHF波108照射。 用EHF波照射局部加热电介质膜，例如PZT膜。 结果，可以改善例如电介质膜的泄漏特性，而不会对形成在Si衬底101上的器件产生不利影响。

公开(公告)号：US06821856B2

公开(公告)日：2004-11-23

申请号：US10188108

申请日：2002-07-03

申请人： Takeshi Takagi

发明人： Takeshi Takagi

IPC分类号： H01L21336

CPC分类号： H01L29/66651 ,  H01L21/76264 ,  H01L21/76283 ,  H01L29/41725 ,  H01L29/458 ,  H01L29/665 ,  H01L29/783 ,  H01L29/78615 ,  H01L29/78618 ,  H01L29/78639

摘要： A semiconductor device comprises an Si substrate, an isolation insulating film formed on the Si substrate, an Si layer formed on the Si substrate, a gate oxide film formed on the Si layer, a gate electrode formed on the gate oxide film, a sidewall formed on the side face of the gate electrode, a gate silicide film formed on the gate electrode, source and drain regions formed at both the sides of the gate electrode and including a part of the Si layer, and a silicide film formed on the source and drain regions. Because the source and drain regions are formed on a layer-insulating film so as to be overlayed, it is possible to decrease the active region and cell area of a device. Thereby, a high-speed operation and high integration can be realized.

摘要翻译： 半导体器件包括Si衬底，形成在Si衬底上的隔离绝缘膜，形成在Si衬底上的Si层，形成在Si层上的栅极氧化膜，形成在栅氧化膜上的栅电极，形成侧壁 在栅电极的侧面上，形成在栅电极上的栅极硅化物膜，形成在栅电极的两侧的源极和漏极区，并且包括一部分Si层，以及形成在源极上的硅化物膜 漏区。 因为源极和漏极区域形成在层间绝缘膜上以便被覆盖，所以可以减小器件的有源区域和单元面积。 由此，能够实现高速运转，高集成化。

公开(公告)号：US06642607B2

公开(公告)日：2003-11-04

申请号：US10061365

申请日：2002-02-04

申请人： Teruhito Ohnishi ,  Takeshi Takagi ,  Akira Asai ,  Taizo Fujii ,  Mitsuo Sugiura ,  Yoshihisa Minami

发明人： Teruhito Ohnishi ,  Takeshi Takagi ,  Akira Asai ,  Taizo Fujii ,  Mitsuo Sugiura ,  Yoshihisa Minami

IPC分类号： H01L2993

CPC分类号： H01L29/93 ,  H01L27/0664 ,  H01L27/0808

摘要： A variable capacitor includes an N+ layer including a variable capacitance region, a P+ layer epitaxially grown on the N+ layer and formed from a SiGe film and a Si film, and a P-type electrode. An NPN-HBT (Hetero-junction Bipolar Transistor) includes a collector diffusion layer formed simultaneously with the N+ layer of the variable capacitor, a collector layer, and a Si/SiGe layer epitaxially grown simultaneously with the P+ layer of the variable capacitor. Since a depletion layer formed in a PN junction of the variable capacitor can extend entirely across the N+ layer, reduction in variation range of the capacitance can be suppressed.

摘要翻译： 可变电容器包括N +层，包括可变电容区，在N +层上外延生长并由SiGe膜和Si膜形成的P +层和P型电极。 NPN-HBT（异质结双极晶体管）包括与可变电容器的N +层同时形成的集电极扩散层，集电极层和与P +层同时外延生长的Si / SiGe层 的可变电容器。 由于形成在可变电容器的PN结中的耗尽层可以完全延伸穿过N +层，所以可以抑制电容的变化范围的减小。

公开(公告)号：USD268371S

公开(公告)日：1983-03-22

申请号：US219721

申请日：1980-12-24

申请人： Yonosuke Iwai ,  Takeshi Takagi

设计人： Yonosuke Iwai ,  Takeshi Takagi

公开(公告)号：USD250210S

公开(公告)日：1978-11-07

申请号：US785149

申请日：1977-04-06

申请人： Takeshi Takagi ,  Hisatane Ohi ,  Yoshio Mizobata

设计人： Takeshi Takagi ,  Hisatane Ohi ,  Yoshio Mizobata

公开(公告)号：US09310342B2

公开(公告)日：2016-04-12

申请号：US13122602

申请日：2009-10-06

申请人： Toshikatsu Sakai ,  Akira Sezaki ,  Takeshi Takagi ,  Takuya Yotani ,  Makoto Takahara ,  Takayuki Oka

发明人： Toshikatsu Sakai ,  Akira Sezaki ,  Takeshi Takagi ,  Takuya Yotani ,  Makoto Takahara ,  Takayuki Oka

IPC分类号： G01N30/24 ,  G01N30/26 ,  G01N30/20 ,  G01N30/88 ,  B01D15/16 ,  G01N30/74

CPC分类号： G01N30/24 ,  B01D15/16 ,  G01N30/26 ,  G01N30/34 ,  G01N30/74 ,  G01N2030/201 ,  G01N2030/202 ,  G01N2030/207 ,  G01N2030/8822

摘要： A liquid chromatography apparatus is provided with a sample preparation unit, a column that separates components of a sample, an eluent supplier that includes a feeder for supplying eluents to the column, a flow path directional valve capable of introducing fixed amounts of the sample and the eluents to the column, an analyzer for analyzing a test solution composed of the sample components separated by the column and one of the eluents, and a controller, wherein the eluent supplier supplies the eluents to the flow path directional valve in an unmixed state. As a result of employing this configuration, analysis time is shortened and eluent consumption is reduced.

摘要翻译： 液相色谱装置具有样品制备单元，分离样品组分的柱，包括用于向柱供给洗脱液的供给器的洗脱液供给器，能够引入固定量的样品的流路切换阀和 用于分析由柱分离的样品组分和洗脱液之一组成的测试溶液的分析器和控制器，其中洗脱剂供体以未混合的状态将洗脱液供应到流路换向阀。 由于采用这种结构，分析时间缩短，洗脱液消耗减少。

公开(公告)号：US20140061579A1

公开(公告)日：2014-03-06

申请号：US13995383

申请日：2012-10-22

申请人： Zhiqiang Wei ,  Takeshi Takagi ,  Koji Katayama

发明人： Zhiqiang Wei ,  Takeshi Takagi ,  Koji Katayama

IPC分类号： H01L45/00 ,  H01L27/24

CPC分类号： H01L45/145 ,  G11C11/5685 ,  G11C13/0007 ,  G11C13/004 ,  G11C13/0069 ,  G11C2013/0073 ,  G11C2013/0083 ,  G11C2213/15 ,  H01L27/101 ,  H01L27/2463 ,  H01L45/08 ,  H01L45/146 ,  H01L45/1625

摘要： A variable resistance nonvolatile memory element includes a first electrode, a second electrode, and a variable resistance layer including: a first oxide layer including a metal oxide having non-stoichiometric composition and including p-type carriers; a second oxide layer located between and in contact with the first oxide layer and a second electrode and including a metal oxide having non-stoichiometric composition and including n-type carriers; an oxygen reservoir region located in the first oxide layer, having no contact with the first electrode, and having an oxygen content atomic percentage higher than that of the first oxide layer; and a local region located in the second oxide layer, having contact with the oxygen reservoir region, and having an oxygen content atomic percentage lower than that of the second oxide layer.

摘要翻译： 可变电阻非易失性存储元件包括第一电极，第二电极和可变电阻层，包括：包含具有非化学计量组成的金属氧化物并包括p型载流子的第一氧化物层; 位于第一氧化物层之间并与第一氧化物层接触的第二氧化物层和第二电极，并且包括具有非化学计量组成并包括n型载体的金属氧化物; 位于所述第一氧化物层中的与第一电极没有接触并且氧含量原子百分比高于第一氧化物层的氧储存区; 以及位于所述第二氧化物层中的与氧储存区接触并且氧含量原子百分比低于第二氧化物层的原子百分比的局部区域。

公开(公告)号：US08559205B2

公开(公告)日：2013-10-15

申请号：US13563321

申请日：2012-07-31

申请人： Takumi Mikawa ,  Takeshi Takagi

发明人： Takumi Mikawa ,  Takeshi Takagi

IPC分类号： G11C17/00

CPC分类号： H01L27/101 ,  G11C13/0007 ,  G11C2213/32 ,  G11C2213/72 ,  G11C2213/73 ,  H01L27/0688 ,  H01L27/112 ,  H01L27/115 ,  H01L27/2409 ,  H01L27/2418 ,  H01L27/2463 ,  H01L27/2481 ,  H01L45/04 ,  H01L45/1233 ,  H01L45/146 ,  H01L45/1683

摘要： A nonvolatile semiconductor memory apparatus including a substrate, lower-layer electrode wires provided on the substrate, an interlayer insulating layer provided with contact holes at locations respectively opposite to the lower-layer electrode wires, resistance variable layers which are respectively connected to the lower-layer electrode wires; and non-ohmic devices which are respectively provided on the resistance variable layers. The non-ohmic devices each has a laminated-layer structure including plural semiconductor layers, a laminated-layer structure including a metal electrode layer and an insulator layer, or a laminated-layer structure including a metal electrode layer and a semiconductor layer. One layer of the laminated-layer structure is embedded to fill each of the contact holes and the semiconductor layer or the insulator layer which is the other layer of the laminated-layer structure has a larger area than an opening of each of the contact holes and is provided on the interlayer insulating layer.

摘要翻译： 一种非易失性半导体存储装置，包括基板，设置在基板上的下层电极布线，在与下层电极布线分别相对的位置设置有接触孔的层间绝缘层，分别与下层电极布线连接的电阻变化层， 层电极线; 以及分别设置在电阻变化层上的非欧姆器件。 非欧姆性器件各自具有包括多个半导体层的层压层结构，包括金属电极层和绝缘体层的层叠层结构，或者包括金属电极层和半导体层的层叠结构。 嵌入层叠层结构的一层以填充每个接触孔，作为层叠层结构的另一层的半导体层或绝缘体层的面积比每个接触孔的开口大， 设置在层间绝缘层上。

公开(公告)号：US08395930B2

公开(公告)日：2013-03-12

申请号：US13596154

申请日：2012-08-28

申请人： Shunsaku Muraoka ,  Takeshi Takagi ,  Satoru Mitani ,  Koji Katayama

发明人： Shunsaku Muraoka ,  Takeshi Takagi ,  Satoru Mitani ,  Koji Katayama

IPC分类号： G11C11/21

CPC分类号： G11C13/0007 ,  G11C13/0069 ,  G11C2013/0083 ,  G11C2213/72 ,  G11C2213/79 ,  H01L45/08 ,  H01L45/1233 ,  H01L45/146 ,  H01L45/1625

摘要： A method includes applying a first polarity writing voltage pulse to a metal oxide layer to change its resistance state from high to low into a write state, applying a second polarity erasing voltage pulse different from the first polarity to the metal oxide layer to change its resistance state from low to high into an erase state, and applying an initial voltage pulse having the second polarity to the metal oxide layer before first application of the writing voltage pulse, to change an initial resistance value of the metal oxide layer. R0>RH>RL and |V0|>|Ve|≧|Vw| are satisfied where R0, RL, and RH are the resistance values of the initial, write, and erase states, respectively, of the metal oxide layer, and V0, Vw, and Ve are voltage values of the initial, writing, and erasing voltage pulses, respectively.

摘要翻译： 一种方法包括：将第一极性写入电压脉冲施加到金属氧化物层，以将其电阻状态从高变为低电平变为写入状态，将不同于第一极性的第二极性擦除电压脉冲施加到金属氧化物层以改变其电阻 状态从低到高进入擦除状态，以及在首次施加写入电压脉冲之前将具有第二极性的初始电压脉冲施加到金属氧化物层，以改变金属氧化物层的初始电阻值。 R0> RH> RL和| V0 |> | Ve |≥| Vw | 满足R0，RL和RH分别是金属氧化物层的初始，写入和擦除状态的电阻值，V0，Vw和Ve是初始，写入和擦除电压的电压值 脉冲。

公开(公告)号：US08339835B2

公开(公告)日：2012-12-25

申请号：US13000243

申请日：2010-04-22

申请人： Zhiqiang Wei ,  Takeshi Takagi ,  Mitsuteru Iijima

发明人： Zhiqiang Wei ,  Takeshi Takagi ,  Mitsuteru Iijima

IPC分类号： G11C11/00

CPC分类号： H01L27/101 ,  G11C13/0002 ,  G11C2213/72 ,  H01L27/24

摘要： A nonvolatile memory element includes a current controlling element having a non-linear current-voltage characteristic, a resistance variable element which changes reversibly between a low-resistance state and a high-resistance state in which a resistance value of the resistance variable element is higher than a resistance value of the resistance variable element in the low-resistance state, in response to voltage pulses applied, and a fuse. The current controlling element, the resistance variable element and the fuse are connected in series, and the fuse is configured to be blown when the current controlling element is substantially short-circuited.

摘要翻译： 非易失性存储元件包括具有非线性电流 - 电压特性的电流控制元件，在电阻可变元件的电阻值较高的低电阻状态与高电阻状态之间可逆地改变的电阻可变元件 比电阻可变元件在低电阻状态下的电阻值，响应于施加的电压脉冲和保险丝。 电流控制元件，电阻可变元件和保险丝串联连接，并且当电流控制元件基本上短路时，保险丝被配置为被熔断。