公开(公告)号：US5512959A

公开(公告)日：1996-04-30

申请号：US255436

申请日：1994-06-08

Applicant: Viviana D'Alto ,  Fabrizio Airoldi ,  Fabio Scalise ,  Maria G. Podesta

Inventor： Viviana D'Alto ,  Fabrizio Airoldi ,  Fabio Scalise ,  Maria G. Podesta

IPC: H04B7/015 ,  H04N5/21

CPC classification number: H04N5/211

Abstract: An adaptive method for suppressing video signal echoes in television equalizers including digital filters having coefficients which are updated in an adaptive and iterative manner using a modified LMS (Least Mean Square) algorithm until the difference, or output error, between a target output signal, called the reference signal, and an outgoing signal from the equalizer is gradually reduced. The method includes the steps of:--applying a "combing" technique to an original filter having K*N coefficients in order to select K comb filters having N coefficients each;--applying said LMS algorithm, with a variable convergence factor to each individual comb filter for a predetermined number of iterations;--gathering the resultant configurations of the comb filter coefficients and selecting a subfilter with N largest modulo coefficients therefrom;--updating the values of said N coefficients again by reiterating the LMS algorithm with variable convergence factor to said subfilter for a limited number of iterations;--clearing all the coefficients with a lower modulo value than a predetermined threshold value;--selecting a group of F coefficients by a slotting operation across those of said coefficients which have a cluster value: and--updating the value of said group of F coefficients, by reiterating the LMS algorithm with variable convergence factor, until the output error becomes smaller than a predetermined value.

Abstract translation: 一种用于抑制电视均衡器中的视频信号回波的自适应方法，其包括具有使用修正的LMS（最小均方根）算法以自适应和迭代方式更新的系数的数字滤波器，直到目标输出信号 参考信号和来自均衡器的输出信号逐渐减小。 该方法包括以下步骤：将“梳理”技术应用于具有K * N个系数的原始滤波器，以便选择每个具有N个系数的K个梳状滤波器; 将具有可变收敛因子的所述LMS算法应用于每个单独梳状滤波器以进行预定次数的迭代; - 梳状滤波器系数的结果配置，并从中选择具有N个最大模数系数的子滤波器; 通过在有限数量的迭代中重复具有可变收敛因子的LMS算法来再次对所述N个系数的值进行重新设置; - 清除具有比预定阈值低的模数值的所有系数; 通过对具有簇值的所述系数的开槽操作选择一组F系数，并且通过重复具有可变收敛因子的LMS算法来更新所述F系数组的值，直到输出误差变小 超过预定值。

公开(公告)号：US5508956A

公开(公告)日：1996-04-16

申请号：US214049

申请日：1994-03-15

Applicant: Giovanni Campardo ,  Giuseppe Crisenza ,  Marco Dallabora

Inventor： Giovanni Campardo ,  Giuseppe Crisenza ,  Marco Dallabora

IPC: G11C17/00 ,  G11C16/04 ,  G11C16/06 ,  G11C16/30 ,  H01L21/8247 ,  H01L27/115 ,  H01L29/788 ,  H01L29/792 ,  G11C11/34

CPC classification number: G11C16/0416 ,  G11C16/04 ,  G11C16/30

Abstract: To reduce the number of depleted cells and the errors caused thereby, the memory array includes groups of control transistors corresponding to groups of memory cells. The control transistors of each group are NMOS transistors having the drain terminal connected to a control line. Each of the control transistors corresponds to a row portion of the memory array. Each control transistor has a control gate connected to a respective word line and a source region connected by a respective source line to the source regions of the memory cells in the same row and group.

Abstract translation: 为了减少耗尽的单元的数量和由此引起的误差，存储器阵列包括对应于存储器单元组的一组控制晶体管。 每组的控制晶体管是具有连接到控制线的漏极端子的NMOS晶体管。 每个控制晶体管对应于存储器阵列的行部分。 每个控制晶体管具有连接到相应字线的控制栅极和由相应源极线连接到相同行和组中的存储器单元的源极区域的源极区域。

公开(公告)号：US5504435A

公开(公告)日：1996-04-02

申请号：US461022

申请日：1995-06-05

Applicant: Romano Perego

Inventor： Romano Perego

IPC: G01R1/04 ,  H05K7/10 ,  H01R23/72 ,  H01F3/02

CPC classification number: H05K7/1023 ,  G01R1/0433

Abstract: A testing contactor is provided for testing small-size semiconductor devices with large currents at high frequencies. Each semiconductor device to be tested has a plurality of leads. The testing contactor includes a plurality of first electric contact elements. A first Kelvin contact for a lead is formed of a first electric contact element in contact with the lead. The testing contactor further includes a plurality of second electric contact elements and a plurality of electric connection elements. An electric connection element in contact with the lead effectively extends the lead. A second Kelvin contact is formed of a second electric contact element and an electric connection element, the second electric contact element in contact with the electric connection element and the electric connection element in contact with the lead.

公开(公告)号：US5495166A

公开(公告)日：1996-02-27

申请号：US45465

申请日：1993-04-08

Applicant: Roberto Alini ,  Andrea Baschirotto ,  Rinaldo Castello ,  Salvatore Portaluri

Inventor： Roberto Alini ,  Andrea Baschirotto ,  Rinaldo Castello ,  Salvatore Portaluri

IPC: H03F1/30 ,  G05F3/24 ,  H03K17/14 ,  G05F3/16

CPC classification number: G05F3/24 ,  H03K17/145

Abstract: A threshold voltage generator for a field-effect transistor, being of a type adapted to compensate for variations of the threshold voltage from a nominal value, comprising a first amplifier having a first input connected to a current generator; a second amplifier connected ahead of a second input of the first amplifier and having an input connected to another current generator; and a third amplifier connected after the first amplifier and having an output adapted to produce the value of said threshold voltage.

Abstract translation: 一种用于场效应晶体管的阈值电压发生器，其类型适于补偿阈值电压与标称值的变化，包括具有连接到电流发生器的第一输入的第一放大器; 连接在第一放大器的第二输入端的第二放大器，并具有连接到另一电流发生器的输入端; 以及连接在所述第一放大器之后并具有适于产生所述阈值电压值的输出端的第三放大器。

公开(公告)号：US5489752A

公开(公告)日：1996-02-06

申请号：US144300

申请日：1993-10-28

Applicant: Carlo Cognetti ,  Michael J. Hundt

Inventor： Carlo Cognetti ,  Michael J. Hundt

IPC: H01L23/367 ,  H01L23/373 ,  H05K1/02 ,  H05K3/30 ,  H05K3/40 ,  H05K1/11

CPC classification number: H05K3/305 ,  H01L23/3677 ,  H01L23/3737 ,  H05K1/0206 ,  H01L2924/15151 ,  H05K2201/0209 ,  H05K2201/09072 ,  H05K2201/09536 ,  H05K2201/0959 ,  H05K2201/09909 ,  H05K2201/10689 ,  H05K3/4069 ,  Y02P70/613 ,  Y10T29/4913 ,  Y10T29/49144

Abstract: A dam is provided on a surface of a circuit board to which an integrated circuit device is to be mounted. The dam defines a region between the integrated circuit package and the circuit board, and a material is injected into this region after the device has been mounted on the circuit board. This material preferably is a good thermal conductor, assisting in the removal of heat from the device. The injected material also preferably acts as an adhesive, more firmly bonding the device the circuit board.

Abstract translation: 在要安装集成电路装置的电路板的表面上设置一个坝。 大坝限定集成电路封装和电路板之间的区域，并且在器件已经安装在电路板上之后将材料注入该区域。 该材料优选是良好的导热体，有助于从装置中除去热量。 注入的材料也优选用作粘合剂，更牢固地将电路板粘合到电路板上。

公开(公告)号：US5485074A

公开(公告)日：1996-01-16

申请号：US112850

申请日：1993-08-26

Applicant: Luciano Tomasini ,  Rinaldo Castello

Inventor： Luciano Tomasini ,  Rinaldo Castello

IPC: H03F3/343 ,  G05F3/26 ,  G05F3/16

CPC classification number: G05F3/26

Abstract: The PSRR (power supply rejection ratio) of a current mirror circuit is increased by cascoding the output transistor of the current mirror, and the precision of the circuit is enhanced by employing a frequency compensated gain stage utilizing a field effect transistor to drive a bipolar current output transistor.

Abstract translation: 电流镜电路的PSRR（电源抑制比）通过级联电流镜的输出晶体管而增加，并且通过采用利用场效应晶体管来驱动双极电流的频率补偿增益级来增强电路的精度 输出晶体管。

公开(公告)号：US5474944A

公开(公告)日：1995-12-12

申请号：US987759

申请日：1992-12-07

Applicant: Raffaele Zambrano

Inventor： Raffaele Zambrano

IPC: H01L21/336 ,  H01L29/423 ,  H01L29/78 ,  H01L21/334

CPC classification number: H01L29/66712 ,  H01L29/7802 ,  H01L29/42368 ,  Y10S148/126

Abstract: A manufacturing process for an integrated circuit which includes at least one vertical-current-flow MOS transistor. The patterned photoresist which screens the body implant is also used to mask the etching of a nitride layer over a pad oxide. After the photoresist is cleared, the nitride pattern is transferred into the oxide, and the resulting oxide/nitride stack is used to mask the source implant. The nitride/oxide stack is then removed, the gate oxide is grown, and the gate layer is then deposited.

Abstract translation: 一种用于集成电路的制造方法，该集成电路包括至少一个垂直电流流量MOS晶体管。 屏蔽体植入物的图案化光致抗蚀剂还用于掩蔽衬垫氧化物上的氮化物层的蚀刻。 在光致抗蚀剂被清除之后，氮化物图案被转移到氧化物中，并且所得到的氧化物/氮化物堆叠用于掩蔽源植入物。 然后去除氮化物/氧化物堆叠，生长栅极氧化物，然后沉积栅极层。

公开(公告)号：US5466622A

公开(公告)日：1995-11-14

申请号：US196634

申请日：1994-02-15

Applicant: Paolo G. Cappelletti

Inventor： Paolo G. Cappelletti

IPC: H01L21/8247 ,  H01L27/115 ,  H01L29/788 ,  H01L29/792

CPC classification number: H01L27/11526 ,  H01L27/11521 ,  H01L27/11541 ,  H01L27/11546 ,  Y10S438/979

Abstract: A process for simultaneously fabricating memory cells, transistors, and diodes for protecting the tunnel oxide layer of the cells, using the DPCC process wherein the first polysilicon layer is not removed from the transistor area, and the gate regions of the transistors are formed by shorted first and second polysilicon layers. To form the diodes, the polyl layer is removed from the active areas in which the diodes are to be formed, using the same mask employed for shaping polyi; the interpoly dielectric layer and the gate oxide layer are removed from the active areas of the diodes, using the same mask employed for removing the dielectric layer from the transistor area; a second polysilicon layer is deposited directly on to the active areas of the diodes; and the poly2 doping ions penetrate the active areas to form N+ regions which, together with the substrate, constitute the protection diodes. The diodes are thus formed prior to shaping poly2, and are connected to the control gates of the cells by the second polycrystalline silicon layer strips forming the word lines.

Abstract translation: 使用DPCC工艺同时制造用于保护电池的隧道氧化物层的存储器单元，晶体管和二极管的工艺，其中第一多晶硅层未从晶体管区域移除，并且晶体管的栅极区域由短路 第一和第二多晶硅层。 为了形成二极管，使用用于成形polyi的相同掩模，从要形成二极管的有源区域中去除多晶硅层; 使用与用于从晶体管区域去除介电层的相同的掩模，从二极管的有源区域去除多晶硅间介质层和栅极氧化物层; 第二多晶硅层直接沉积到二极管的有源区上; 并且poly2掺杂离子穿透有源区域以形成N +区域，其与衬底一起构成保护二极管。 因此在形成poly2之前形成二极管，并且通过形成字线的第二多晶硅层条连接到电池的控制栅极。

公开(公告)号：US5459787A

公开(公告)日：1995-10-17

申请号：US95752

申请日：1993-07-21

Applicant: Luciano Tomasini ,  Rinaldo Castello ,  Pietro Erratico

Inventor： Luciano Tomasini ,  Rinaldo Castello ,  Pietro Erratico

IPC: H04B1/58 ,  H04M1/58 ,  H04M1/76

CPC classification number: H04M1/585 ,  H04B1/586 ,  H04M1/76

Abstract: A circuit for synthesizing an impedance associated with a telephone subscriber's circuit connected to a two-wire telephone line is described. The circuit of the invention is adapted to synthesize a complex impedance which can function both as a termination impedance and a balance impedance. The termination impedance utilizes a positive feedback loop structure having a loop gain which is at all times less than unity. The circuit that implements both the termination and balance impedances with sidetone suppression is also described. Each of the embodiments is realizable with a single external component consisting of a resistor.

Abstract translation: 描述用于合成与连接到两线电话线路的电话用户电路相关联的阻抗的电路。 本发明的电路适于合成可以起到终端阻抗和平衡阻抗的复阻抗。 终端阻抗利用正反馈环路结构，其具有始终小于1的环路增益。 还描述了同时实现端接抑制和平衡阻抗的电路。 每个实施例都可以由一个由电阻组成的单个外部元件来实现。

公开(公告)号：US5407861A

公开(公告)日：1995-04-18

申请号：US68139

申请日：1993-05-26

Applicant: Maria S. Marangon ,  Andrea Marmiroli ,  Giorgio Desanti

Inventor： Maria S. Marangon ,  Andrea Marmiroli ,  Giorgio Desanti

IPC: H01L21/28 ,  H01L21/768 ,  H01L21/44

CPC classification number: H01L21/76877 ,  H01L21/76838 ,  H01L21/7684 ,  Y10S438/963 ,  Y10S438/97 ,  Y10S438/974

Abstract: A plug contact process wherein, after contact holes are etched, an adhesion layer (such as Ti/TiN) and a filler metal (such as tungsten) are deposited overall. A two-stage etch is then used: First, the filler metal is etched preferentially with respect to the adhesion layer, until an endpoint signal first indicates that said adhesion layer is exposed. No overetch is used at this stage. Thereafter a nonpreferential etch is used to clear residues of the filler metal, while also uniformly reducing the height of the adhesion layer. This prevents the tops of the plugs in the contact holes from being recessed. Aluminum (or other metal) is then deposited and patterned (using a stack etch to remove the undesired portions of the adhesion layer too) to implement the desired wiring pattern. This process thereby reduces voids, and resulting metallization defects, in a process with high-aspect-ratio contacts. In addition, the residual adhesion layer helps to reduce electromigration.

Abstract translation: 一种插头接触方法，其中在接触孔被蚀刻之后，整体上沉积粘合层（例如Ti / TiN）和填充金属（例如钨）。 然后使用两级蚀刻：首先，相对于粘合层优先蚀刻填充金属，直到端点信号首先指示所述粘合层暴露。 在这个阶段没有使用过筛。 此后，使用非优选蚀刻来清除填充金属的残留物，同时也均匀地降低粘附层的高度。 这防止了接触孔中的插塞的顶部凹陷。 然后将铝（或其他金属）沉积并图案化（使用叠层蚀刻以除去粘附层的不希望的部分），以实现所需的布线图案。 因此，在具有高纵横比接触的过程中，该过程减少了空隙以及所得到的金属化缺陷。 另外，残留粘附层有助于减少电迁移。