公开(公告)号：US06549464B2

公开(公告)日：2003-04-15

申请号：US10187285

申请日：2002-07-02

申请人： Tomoharu Tanaka ,  Hiroshi Nakamura ,  Ken Takeuchi ,  Riichiro Shirota ,  Fumitaka Arai ,  Susumu Fujimura

发明人： Tomoharu Tanaka ,  Hiroshi Nakamura ,  Ken Takeuchi ,  Riichiro Shirota ,  Fumitaka Arai ,  Susumu Fujimura

IPC分类号： G11C1604

CPC分类号： G11C16/0483 ,  G11C11/5621 ,  G11C11/5628 ,  G11C11/5635 ,  G11C16/3404 ,  G11C16/3409 ,  G11C16/344 ,  G11C16/3445 ,  G11C16/345 ,  G11C16/3454 ,  G11C16/3459 ,  G11C16/3463 ,  G11C2211/5621

摘要： A NAND cell unit comprising a plurality of memory cells which are connected in series. An erase operation is effected on all memory cells. Then, a soft-program voltage, which is opposite in polarity to the erase voltage applied in the erase operation, is applied to all memory cells, thereby setting all memory cells out of an over-erased state. Thereafter, a program voltage of 20V is applied to the control gate of any selected one of the memory cells, 0V is applied to the control gates of the two memory cells provided adjacent to the selected memory cell, and 11V is applied to the control gates of the remaining memory cells. Data is thereby programmed into the selected memory cell. The time for which the program voltage is applied to the selected memory cell is adjusted in accordance with the data to be programmed into the selected memory cell. Hence, data “0” can be correctly programmed into the selected memory cell, multi-value data can be read from any selected memory cell at high speed.

公开(公告)号：US5940325A

公开(公告)日：1999-08-17

申请号：US971975

申请日：1997-11-17

申请人： Shang-De Chang ,  Jai-Hwang Chang ,  Edwin Chow

发明人： Shang-De Chang ,  Jai-Hwang Chang ,  Edwin Chow

IPC分类号： G11C16/04 ,  G11C16/02 ,  G11C16/10 ,  G11C16/14 ,  G11C16/16 ,  G11C16/34 ,  G11C17/00 ,  H01L21/8247 ,  H01L27/115 ,  H01L29/788 ,  H01L29/792 ,  G11C7/00 ,  H01L29/78

CPC分类号： G11C16/345 ,  G11C16/0416 ,  G11C16/10 ,  G11C16/14 ,  G11C16/16 ,  G11C16/3404 ,  G11C16/3409 ,  G11C16/3445 ,  G11C16/3459 ,  H01L27/115 ,  H01L29/7883

摘要： A single transistor electrically erasable programmable memory device capable of being programmed and erased using Fowler-Nordheim tunneling and capable of being operated using low voltages. Portions of each of the source and drain regions overlap with the first gate dielectric layer, and the interpoly dielectric layer is chosen to have a high dielectric constant so as to maximize the capacitive coupling ratio between floating gate, control gate, source, and drain. The logical condition of cells in the array is set by first elevating a block of cells to a high voltage threshold and by individually lowering the voltage threshold of selected cells.

摘要翻译： 能够使用Fowler-Nordheim隧道进行编程和擦除并能够使用低电压操作的单晶体管电可擦除可编程存储器件。 源极和漏极区域中的每一个的部分与第一栅极介电层重叠，并且选择互互电介质层以具有高的介电常数，以便最大化浮动栅极，控制栅极，源极和漏极之间的电容耦合比。 通过首先将单元格块升高到高电压阈值并单独降低所选单元格的电压阈值来设置阵列中单元格的逻辑状态。

公开(公告)号：US5687120A

公开(公告)日：1997-11-11

申请号：US534700

申请日：1995-09-27

申请人： Shang-De Chang ,  Jia-Hwang Chang ,  Edwin Chow

发明人： Shang-De Chang ,  Jia-Hwang Chang ,  Edwin Chow

IPC分类号： G11C16/04 ,  G11C16/02 ,  G11C16/10 ,  G11C16/14 ,  G11C16/16 ,  G11C16/34 ,  G11C17/00 ,  H01L21/8247 ,  H01L27/115 ,  H01L29/788 ,  H01L29/792 ,  G11C7/00 ,  G11C11/40

CPC分类号： G11C16/345 ,  G11C16/0416 ,  G11C16/10 ,  G11C16/14 ,  G11C16/16 ,  G11C16/3404 ,  G11C16/3409 ,  G11C16/3445 ,  G11C16/3459 ,  H01L27/115 ,  H01L29/7883

摘要： A single transistor electrically erasable programmable memory device capable of being programmed and erased using Fowler-Nordheim tunneling and capable of being operated using low voltages. Portions of each of the source and drain regions overlap with the first gate dielectric layer, and the interpoly dielectric layer is chosen to have a high dielectric constant so as to maximize the capacitive coupling ratio between floating gate, control gate, source, and drain. The logical condition of cells in the array is set by first elevating a block of cells to a high voltage threshold and by individually lowering the voltage threshold of selected cells.

摘要翻译： 能够使用Fowler-Nordheim隧道进行编程和擦除并能够使用低电压操作的单晶体管电可擦除可编程存储器件。 源极和漏极区域中的每一个的部分与第一栅极介电层重叠，并且选择互互电介质层以具有高的介电常数，以便最大化浮动栅极，控制栅极，源极和漏极之间的电容耦合比。 通过首先将单元格块升高到高电压阈值并单独降低所选单元格的电压阈值来设置阵列中单元格的逻辑状态。

公开(公告)号：US5625591A

公开(公告)日：1997-04-29

申请号：US445960

申请日：1995-05-22

申请人： Hideo Kato ,  Nobutake Sugiura ,  Kiyotaka Uchigane ,  Masamichi Asano

发明人： Hideo Kato ,  Nobutake Sugiura ,  Kiyotaka Uchigane ,  Masamichi Asano

IPC分类号： G11C8/08 ,  G11C16/16 ,  G11C16/28 ,  G11C16/34 ,  G11C29/50 ,  G11C29/00

CPC分类号： G11C16/345 ,  G11C16/16 ,  G11C16/28 ,  G11C16/344 ,  G11C29/028 ,  G11C29/50 ,  G11C29/50004 ,  G11C29/50012 ,  G11C8/08 ,  G06F2201/81 ,  G11C16/04 ,  G11C2029/5004

摘要： When an erase voltage is applied to the sources of data erasable and rewritable memory cells each having a floating gate, the erasure characteristics of the memory cells can be improved by controlling the rise time of the erase voltage or by increasing the erase voltage stepwise. In test mode, no row lines are selected by a row decoder and further the sources of the respective memory cells are set to ground level. Under these conditions, in case there exists an overerased memory cell, this cell is turned on due to depletion, so that it is possible to detect the presence of the overerased memory cell on the basis of change in potential of the column line connected to this turned on memory cell. A differential amplifier is used to detect the change in potential of the column line. In the test mode, the potential of the column lines is compared with a reference potential applied to a dummy column line, and a source bias generating circuit applies a test potential suitable for test to the respective sources of the cells, to shift the threshold level of the respective cells in a positive direction, for instance. By applying this test potential to the cells, it is possible to detect the pseudo-threshold level shifted in the positive direction; that is, to detect the overerased status of the memory cell more properly. Further, the erasure is effected until the threshold level of a memory cell of the highest erasure speed reaches a predetermined level, irrespective of the threshold distribution width of the memory cells, thus realizing a higher speed access to the device of narrower threshold distribution width, as compared with the conventional device.

摘要翻译： 当擦除电压施加到每个具有浮动栅极的数据可擦除和可重写存储单元的源时，可以通过控制擦除电压的上升时间或逐步增加擦除电压来提高存储器单元的擦除特性。 在测试模式下，行解码器不选择行行，并且进一步将各存储单元的源设置为地电平。 在这些条件下，在存在过度存储单元的情况下，该单元由于耗尽而导通，从而可以基于连接到该存储单元的列线的电位变化来检测过度存储存储单元的存在 打开内存单元。 差分放大器用于检测列线的电位变化。 在测试模式中，将列线的电位与施加到虚拟列线的参考电位进行比较，并且源偏置产生电路将适合于测试的测试电位施加到单元的各个源，以将阈值电平 例如，各个单元的正方向。 通过将该测试电位施加到单元，可以检测正向偏移的伪阈值电平; 也就是说，更正确地检测存储器单元的过渡状态。 此外，擦除是直到最高擦除速度的存储单元的阈值水平达到预定水平，而不管存储器单元的阈值分布宽度如何，从而实现对较窄阈值分布宽度的设备的更高速度访问， 与常规装置相比。

公开(公告)号：US5587947A

公开(公告)日：1996-12-24

申请号：US534691

申请日：1995-09-27

申请人： Shang-De Chang ,  Jia-Hwang Chang ,  Edwin Chow

发明人： Shang-De Chang ,  Jia-Hwang Chang ,  Edwin Chow

IPC分类号： G11C16/04 ,  G11C16/02 ,  G11C16/10 ,  G11C16/14 ,  G11C16/16 ,  G11C16/34 ,  G11C17/00 ,  H01L21/8247 ,  H01L27/115 ,  H01L29/788 ,  H01L29/792 ,  G11C7/00

CPC分类号： G11C16/345 ,  G11C16/0416 ,  G11C16/10 ,  G11C16/14 ,  G11C16/16 ,  G11C16/3404 ,  G11C16/3409 ,  G11C16/3445 ,  G11C16/3459 ,  H01L27/115 ,  H01L29/7883

摘要： A single transistor electrically erasable programmable memory device capable of being programmed and erased using Fowler-Nordheim tunneling and capable of being operated using low voltages. Portions of each of the source and drain regions overlap with the first gate dielectric layer, and the interpoly dielectric layer is chosen to have a high dielectric constant so as to maximize the capacitive coupling ratio between floating gate, control gate, source, and drain. The logical condition of cells in the array is set by first elevating a block of cells to a high voltage threshold and by individually lowering the voltage threshold of selected cells.

摘要翻译： 能够使用Fowler-Nordheim隧道进行编程和擦除并能够使用低电压操作的单晶体管电可擦除可编程存储器件。 源极和漏极区域中的每一个的部分与第一栅极介电层重叠，并且选择互互电介质层以具有高的介电常数，以便最大化浮动栅极，控制栅极，源极和漏极之间的电容耦合比。 通过首先将单元格块升高到高电压阈值并单独降低所选单元格的电压阈值来设置阵列中单元格的逻辑状态。

公开(公告)号：US5371706A

公开(公告)日：1994-12-06

申请号：US932462

申请日：1992-08-20

申请人： Steven V. Krentz ,  David A. Tatman

发明人： Steven V. Krentz ,  David A. Tatman

IPC分类号： G11C16/34 ,  G11C7/00

CPC分类号： G11C16/345 ,  G11C16/344

摘要： The circuit and method of this invention provide for rapid and reliable detection of depleted or nearly-depleted cells in a column. The circuit is formed on the substrate of a nonvolatile, integrated-circuit memory including rows and columns of memory cells. The drain of each memory cell is connected to a drain-column line and the control gate that is connected to a wordline. One input of a sense amplifier is connected to the drain-column line. The other input of the sense amplifier is connected to a current reference formed on said substrate. The wordline is connected to a wordline test voltage and the output of the sense amplifier is coupled to an output pin of the integrated circuit. The current through the drain-column line is compared with the current through the current reference and, if the current through the drain-column line is sufficiently close to the current through said current reference, a signal is transmitted to an output pin of the integrated circuit.

摘要翻译： 本发明的电路和方法提供了对柱中耗尽或几乎耗尽的细胞的快速和可靠的检测。 电路形成在包括行和列的存储器单元的非易失性集成电路存储器的基板上。 每个存储单元的漏极连接到漏极 - 列线路，并连接到字线的控制栅极。 读出放大器的一个输入端连接到漏 - 列线。 读出放大器的另一个输入端与形成在所述衬底上的电流基准相连。 字线连接到字线测试电压，读出放大器的输出耦合到集成电路的输出引脚。 将通过漏极 - 列线路的电流与通过电流基准的电流进行比较，并且如果通过漏 - 列线路的电流足够接近通过所述电流基准的电流，则信号被发送到集成的 电路。

公开(公告)号：US4841482A

公开(公告)日：1989-06-20

申请号：US157364

申请日：1988-02-17

申请人： Jerry A. Kreifels ,  George Hoekstra

发明人： Jerry A. Kreifels ,  George Hoekstra

IPC分类号： G11C16/34 ,  G11C29/02 ,  G11C29/50

CPC分类号： G11C16/345 ,  G11C16/344 ,  G11C29/02 ,  G11C29/025 ,  G11C29/50 ,  G11C16/04 ,  G11C2029/5006

摘要： A circuit and method for verifying leakage in a flash EPROM/EEPROM memory cell which is fabricated on a silicon substrate having floating gate. A word line coupled to the control gate of the memory cell is typically at ground potential, but during a test mode a positive voltage is placed on the control gate and leakage current at the drain is measured. A good cell will typically have zero or negligible drain leakage current, however, a cell which is susceptible to being overerased will exhibit appreciable leakage current. A circuit is implemented on the chip with the memory for switching a positive voltage onto the word line during the test mode.

摘要翻译： 一种用于验证在具有浮动栅极的硅衬底上制造的闪存EPROM / EEPROM存储单元中的泄漏的电路和方法。 耦合到存储单元的控制栅极的字线通常处于地电位，但是在测试模式期间，在控制栅极上放置正电压，并测量漏极处的漏电流。 良好的电池通常具有零或可忽略的漏极漏电流，然而，容易被过度烧蚀的电池将会呈现明显的漏电流。 在芯片上实现一个电路，用于在测试模式期间将正电压切换到字线上的存储器。

公开(公告)号：US10062418B2

公开(公告)日：2018-08-28

申请号：US14997575

申请日：2016-01-18

申请人： PHISON ELECTRONICS CORP.

发明人： Chih-Kang Yeh

IPC分类号： G11C7/00 ,  G06F11/10 ,  G11C29/52 ,  G06F3/06 ,  G06F12/02 ,  G11C16/34 ,  G11C29/42 ,  G11C11/56

CPC分类号： G11C7/00 ,  G06F3/0679 ,  G06F11/1068 ,  G06F12/0246 ,  G11C5/005 ,  G11C7/1006 ,  G11C11/5628 ,  G11C16/0483 ,  G11C16/10 ,  G11C16/345 ,  G11C29/42 ,  G11C29/52

摘要： A data programming method and a memory storage device are provided. The method includes: programming a plurality of first type physical units in a rewritable non-volatile memory module to store first data; encoding the first data to generate encoded data; receiving second data; and programming at least one of a plurality of second type physical units in the rewritable non-volatile memory module corresponding to the first type physical units to store at least a part of the second data after the first data is encoded. Therefore, the correcting ability for correcting errors in pair physical units in multi-channel programming procedure may be improved.

公开(公告)号：US09870828B2

公开(公告)日：2018-01-16

申请号：US15277992

申请日：2016-09-27

申请人： Winbond Electronics Corp.

发明人： Katsutoshi Suito ,  Riichiro Shirota

IPC分类号： G11C16/14 ,  G11C16/34 ,  G11C16/10 ,  G11C16/04 ,  H01L27/11524

CPC分类号： G11C16/14 ,  G11C16/0483 ,  G11C16/344 ,  G11C16/3445 ,  G11C16/345 ,  G11C16/3459 ,  G11C16/3472 ,  G11C16/3477 ,  H01L27/11524

摘要： An erasing method of a nonvolatile semiconductor memory device of the disclosure includes erasing data of a selected memory cell (step S100); immediately applying a programming voltage lower than a programming voltage in a programming time to all control gates of the selected memory cell after the erasing step, thereby performing a week programming (step S110); performing a erasing verification of the selected memory cell (step S120).

公开(公告)号：US09431114B2

公开(公告)日：2016-08-30

申请号：US14695849

申请日：2015-04-24

申请人： SK hynix Inc.

发明人： Tai Kyu Kang

IPC分类号： G11C16/04 ,  G11C16/14 ,  G11C16/26 ,  G11C16/34 ,  G11C16/08 ,  G11C16/10

CPC分类号： G11C16/14 ,  G11C16/0483 ,  G11C16/08 ,  G11C16/10 ,  G11C16/16 ,  G11C16/26 ,  G11C16/32 ,  G11C16/344 ,  G11C16/3445 ,  G11C16/345

摘要： A method of operating a semiconductor device includes dividing an operation of the semiconductor device into a plurality of periods, and determining a plurality of state codes respectively corresponding to the periods; performing the operation according to a received command; when a pause command is received, pausing the operation and storing a state code of the plurality of state codes corresponding to a paused period among the plurality of periods; and performing the operation starting from a period determined according to the stored state code when a resumption command is received.

摘要翻译： 一种操作半导体器件的方法包括将半导体器件的操作划分成多个周期，以及分别对应于这些周期来确定多个状态代码; 根据接收到的命令执行操作; 当接收到暂停命令时，暂停所述操作并存储与所述多个周期中的暂停期间对应的所述多个状态码的状态码; 以及当接收到恢复命令时，从根据所存储的状态代码确定的时段开始执行操作。