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    Fold interleaver
    111.
    发明授权
    Fold interleaver 失效
    折叠交织器

    公开(公告)号：US06563641B2

    公开(公告)日：2003-05-13

    申请号：US09892224

    申请日：2001-06-25

    Applicant: Bin Zhao

    Inventor： Bin Zhao

    IPC: G02B530

    CPC classification number: G02B6/29302 ,  G02B6/272 ,  G02B6/2766 ,  G02B6/2773 ,  G02B6/29386 ,  Y10S359/90

    Abstract: An interleaver has a birefringent element assembly and a reflector configured so as to direct light from the birefringent element assembly back into and through birefringent element assembly. The birefringent element assembly has at least one birefringent element. Directing light from the birefringent element assembly back through the birefringent element assembly enhances transmission characteristics and/or mitigates dispersion.

    Abstract translation: 交织器具有双折射元件组件和反射器，其被配置为将来自双折射元件组件的光引导回并穿过双折射元件组件。 双折射元件组件具有至少一个双折射元件。 将来自双折射元件组件的光引导回通过双折射元件组件增强透射特性和/或减轻分散。

    Dual-damascene interconnect structures and methods of fabricating same
    113.
    发明授权
    Dual-damascene interconnect structures and methods of fabricating same 有权
    双镶嵌互连结构及其制造方法

    公开(公告)号：US06417094B1

    公开(公告)日：2002-07-09

    申请号：US09224339

    申请日：1998-12-31

    Applicant: Bin Zhao ,  Liming Tsau

    Inventor： Bin Zhao ,  Liming Tsau

    IPC: H01L214763

    CPC classification number: H01L21/76831 ,  H01L21/76808 ,  H01L2221/1031

    Abstract: An interconnect fabrication process and structure provides barrier enhancement at the via sidewalls and improved capability to fabricate high aspect ratio dual damascene interconnects. A via structure is patterned into the via dielectric first, then a dielectric barrier (for example, anisotropically etched silicon nitride) is formed only along the via sidewalls in the dual damascene structure prior to deposition of a metal barrier (for example, Ta/TaN). In this way, the effective barrier thickness along the bottom of the via is increased, eliminating the structure's susceptibility to metal migration. The absence of dielectric barrier along the interconnect trench sidewalls leads to low interconnect resistance and low interconnect capacitance. The present invention also provides an improved fabrication method for obtaining high aspect ratio dual damascene interconnect structures.

    Abstract translation: 互连制造工艺和结构在通孔侧壁提供了屏障增强，并提高了制造高纵横比双镶嵌互连的能力。 通孔结构首先被图案化到通孔电介质中，然后在沉积金属屏障（例如，Ta / TaN）之前仅在双镶嵌结构中沿着通孔侧壁形成介电阻挡层（例如各向异性蚀刻的氮化硅） ）。 通过这种方式，沿着通孔底部的有效阻挡层厚度增加，消除了结构对金属迁移的敏感性。 沿着互连沟槽侧壁不存在电介质阻挡层导致低互连电阻和低互连电容。 本发明还提供了一种用于获得高纵横比的双镶嵌互连结构的改进的制造方法。

    Interconnect structure and method employing air gaps between metal lines and between metal layers
    114.
    发明授权
    Interconnect structure and method employing air gaps between metal lines and between metal layers 有权
    互连结构和方法采用金属线之间和金属层之间的气隙

    公开(公告)号：US06211561B1

    公开(公告)日：2001-04-03

    申请号：US09193499

    申请日：1998-11-16

    Applicant: Bin Zhao

    Inventor： Bin Zhao

    IPC: H01L2900

    CPC classification number: H01L23/5222 ,  H01L21/7682 ,  H01L23/4821 ,  H01L23/5329 ,  H01L2924/0002 ,  H01L2924/00

    Abstract: An interconnect structure and fabrication method are provided to form air gaps between interconnect lines and between interconnect layers. A conductive material is deposited and patterned to form a first level of interconnect lines. A first dielectric layer is deposited over the first level of interconnect lines. One or more air gaps are formed in the first dielectric layer to reduce inter-layer capacitance, intra-layer capacitance or both inter-layer and intra-layer capacitance. At least one support pillar remains in the first dielectric layer to promote mechanical strength and thermal conductivity. A sealing layer is deposited over the first insulative layer to seal the air gaps. Via holes are patterned and etched through the sealing layer and the first dielectric layer. A conductive material is deposited to fill the via holes and form conductive plugs therein. Thereafter, a conductive material is deposited and patterned to form a second level of interconnect lines.

    Abstract translation: 提供互连结构和制造方法以在互连线之间和互连层之间形成气隙。 导电材料被沉积并图案化以形成第一级互连线。 第一介电层沉积在第一级互连线上。 在第一介电层中形成一个或多个空气间隙，以减少层间电容，层间电容或层间电容和层间电容。 至少一个支撑柱保留在第一介电层中以促进机械强度和导热性。 密封层沉积在第一绝缘层上以密封气隙。 图案化通孔并通过密封层和第一介电层蚀刻。 沉积导电材料以填充通孔并在其中形成导电塞。 此后，沉积并图案化导电材料以形成第二级互连线。

    Bonding pad and support structure and method for their fabrication
    115.
    发明授权
    Bonding pad and support structure and method for their fabrication 有权
    接合垫和支撑结构及其制造方法

    公开(公告)号：US06198170B1

    公开(公告)日：2001-03-06

    申请号：US09465532

    申请日：1999-12-16

    Applicant: Bin Zhao

    Inventor： Bin Zhao

    IPC: H01L2348

    CPC classification number: H01L24/05 ,  H01L24/03 ,  H01L2224/02166 ,  H01L2224/04042 ,  H01L2224/05093 ,  H01L2224/05556 ,  H01L2224/05647 ,  H01L2224/45124 ,  H01L2224/45144 ,  H01L2224/48647 ,  H01L2224/48747 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01015 ,  H01L2924/01019 ,  H01L2924/01023 ,  H01L2924/01027 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01039 ,  H01L2924/01063 ,  H01L2924/01068 ,  H01L2924/01073 ,  H01L2924/01074 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01084 ,  H01L2924/04953 ,  H01L2924/05042 ,  H01L2924/14 ,  H01L2924/30105 ,  H01L2924/00

    Abstract: A copper bonding pad is directly supported by a copper via pad structure, the copper via pad structure having substantially the same geometry and dimensions as the copper bonding pad. The combination of the copper bonding pad and the copper via pad structure results in an increase in effective thickness of the copper bonding pad. Due to this effective increase in the bonding pad thickness, the bonding pad is more tolerant to the potential dishing problem caused by the CMP process. Additional metal pad structures and via pad structures are used below the bonding pad. The additional metal pad structures and via pad structures comprise alternating segments of interconnect metal and dielectric fillers, and alternating segments of via metal and dielectric fillers, respectively. The alternating segments of interconnect metal and dielectric fillers and the alternating segments of via metal and dielectric fillers prevent or reduce the potential dishing problem that otherwise exists in damascene and CMP processing. The alternating segments of interconnect metal and dielectric fillers and the alternating segments of via metal and dielectric fillers are arranged such that there are a number of columns of solid metal support under the bonding pad. The columns of solid metal support significantly improve the poor mechanical support otherwise provided by the low dielectric constant materials that are presently used in fabrication of modern copper integrated circuits. The columns of solid metal support also improve thermal conductivity of the bonding pad.

    Abstract translation: 铜焊盘由铜通孔焊盘结构直接支撑，铜通孔焊盘结构具有与铜焊盘基本上相同的几何形状和尺寸。 铜焊盘和铜通孔焊盘结构的组合导致铜焊盘的有效厚度的增加。 由于焊盘厚度的这种有效增加，焊盘更能承受由CMP工艺引起的潜在的凹陷问题。 在焊盘下面使用附加的金属焊盘结构和通孔焊盘结构。 附加的金属焊盘结构和通孔焊盘结构分别包括互连金属和介电填料的交替段，以及通孔金属和电介质填料的交替段。 互连金属和电介质填料的交替段和通孔金属和电介质填料的交替段防止或减少在镶嵌和CMP加工中存在的潜在凹陷问题。 互连金属和电介质填料的交替段和通孔金属和电介质填料的交替段布置成使得在接合焊盘下方有许多固体金属支撑柱。 固体金属载体的柱显着地改善了目前用于制造现代铜集成电路的低介电常数材料提供的差的机械支撑。 固体金属载体的柱也提高了焊盘的导热性。

    Methods for forming high-performing dual-damascene interconnect structures
    116.
    发明授权
    Methods for forming high-performing dual-damascene interconnect structures 有权
    用于形成高性能双镶嵌互连结构的方法

    公开(公告)号：US6071809A

    公开(公告)日：2000-06-06

    申请号：US161176

    申请日：1998-09-25

    Applicant: Bin Zhao

    Inventor： Bin Zhao

    IPC: H01L21/768 ,  H01L23/522 ,  H01L23/532 ,  H01L21/4763

    CPC classification number: H01L21/7681 ,  H01L21/76819 ,  H01L21/7684 ,  H01L23/5222 ,  H01L23/5329 ,  H01L2924/0002

    Abstract: Dual damascene methods and structures are provided for IC interconnects which use a dual-damascene process incorporating a low-k dielectric material, high conductivity metal, and an improved hard mask scheme. A pair of hard masks are employed: a silicon dioxide layer and a silicon nitride layer, wherein the silicon dioxide layer acts to protect the silicon nitride layer during dual damascene etch processing, but is subsequently sacrificed during CMP, allowing the silicon nitride layer to act as a the CMP hard mask. In this way, delamination of the low-k material is prevented, and any copper-contaminated silicon dioxide material is removed.

    Abstract translation: 提供了双重镶嵌方法和结构用于IC互连，其使用结合低k电介质材料，高导电性金属和改进的硬掩模方案的双镶嵌工艺。 使用一对硬掩模：二氧化硅层和氮化硅层，其中二氧化硅层用于在双镶嵌蚀刻处理期间保护氮化硅层，但随后在CMP期间被牺牲，允许氮化硅层起作用 作为CMP硬掩模。 以这种方式，可以防止低k材料的分层，并且去除任何铜污染的二氧化硅材料。

    Protected encapsulation of catalytic layer for electroless copper interconnect
    117.
    发明授权
    Protected encapsulation of catalytic layer for electroless copper interconnect 失效
    用于无电铜互连的催化层的保护封装

    公开(公告)号：US5824599A

    公开(公告)日：1998-10-20

    申请号：US587264

    申请日：1996-01-16

    Applicant: Yosef Schacham-Diamand ,  Valery M. Dubin ,  Chiu H. Ting ,  Bin Zhao ,  Prahalad K. Vasudev ,  Melvin Desilva

    Inventor： Yosef Schacham-Diamand ,  Valery M. Dubin ,  Chiu H. Ting ,  Bin Zhao ,  Prahalad K. Vasudev ,  Melvin Desilva

    IPC: H01L21/768 ,  H01L21/44

    CPC classification number: H01L21/76834 ,  H01L21/76838 ,  H01L21/76843 ,  H01L21/76874 ,  H01L21/76858 ,  Y10S977/712 ,  Y10S977/81 ,  Y10S977/888 ,  Y10S977/89

    Abstract: A method for utilizing electroless copper deposition to form interconnects on a semiconductor. Once a via or a trench is formed in a dielectric layer, a titanium nitride (TiN) or tantalum (Ta) barrier layer is deposited. Then, a catalytic copper seed layer is conformally blanket deposited in vacuum over the barrier layer. Next, without breaking the vacuum, an aluminum protective layer is deposited onto the catalytic layer to encapsulate and protect the catalytic layer from oxidizing. An electroless deposition technique is then used to auto-catalytically deposit copper on the catalytic layer. The electroless deposition solution dissolves the overlying protective layer to expose the surface of the underlying catalytic layer. The electroless copper deposition occurs on this catalytic surface, and continues until the via/trench is filled. Subsequently, the copper and barrier material are polished by an application of chemical-mechanical polishing (CMP) to remove excess copper and barrier material from the surface, so that the only copper and barrier material remaining are in the via/trench openings. Then an overlying silicon nitride (SiN) layer is formed above the exposed copper in order to form a dielectric barrier layer. The copper interconnect is fully encapsulated from the adjacent material by the TiN (or Ta) barrier layer and the overlying SiN layer.

    Abstract translation: 一种利用无电铜沉积在半导体上形成互连的方法。 一旦在电介质层中形成通孔或沟槽，则沉积氮化钛（TiN）或钽（Ta）阻挡层。 然后，催化铜籽晶层在真空中在阻挡层上共形地覆盖。 接下来，在不破坏真空的情况下，将铝保护层沉积到催化剂层上以包封并保护催化剂层免于氧化。 然后使用无电沉积技术在催化剂层上自动催化沉积铜。 无电沉积溶液溶解上覆的保护层以暴露下面的催化剂层的表面。 无电铜沉积发生在该催化剂表面上，并持续直到通孔/沟槽被填充。 随后，通过施加化学机械抛光（CMP）来抛光铜和阻挡材料，以从表面去除多余的铜和阻挡材料，使得剩余的唯一的铜和阻挡材料在通孔/沟槽开口中。 然后，在暴露的铜上方形成覆盖氮化硅（SiN）层，以形成电介质阻挡层。 铜互连通过TiN（或Ta）阻挡层和覆盖的SiN层从相邻材料完全封装。

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