公开(公告)号：US20190027497A1

公开(公告)日：2019-01-24

申请号：US15746687

申请日：2017-07-07

Applicant: BOE Technology Group Co., Ltd.

Inventor： Chunping Long ,  Pan Li

IPC: H01L27/12 ,  G02F1/1362 ,  G02F1/1343 ,  G02F1/1368

Abstract: An array substrate and a display are provided. The array substrate includes a plurality of sub-pixel regions arranged in rows and columns. The sub-pixel region includes a pixel aperture region. A conductive pattern is provided between two adjacent sub-pixel regions in a row direction, at least part of the conductive pattern being located between pixel aperture regions of the two adjacent sub-pixel regions in the row direction, and the conductive pattern being connected to a common voltage.

公开(公告)号：US10084095B2

公开(公告)日：2018-09-25

申请号：US15322490

申请日：2016-03-01

Applicant: BOE TECHNOLOGY GROUP CO., LTD.

Inventor： Xiaolong Li ,  Zheng Liu ,  Xiaoyong Lu ,  Chunping Long ,  Huijuan Zhang

IPC: H01L31/0312 ,  H01L29/786 ,  H01L29/04 ,  H01L29/16 ,  H01L29/66 ,  H01L21/04 ,  H01L21/02

CPC classification number: H01L29/78609 ,  H01L21/02527 ,  H01L21/02598 ,  H01L21/02609 ,  H01L21/0262 ,  H01L21/02664 ,  H01L21/043 ,  H01L29/045 ,  H01L29/1602 ,  H01L29/66045 ,  H01L29/66742 ,  H01L29/78621 ,  H01L29/78684 ,  H01L29/78696

Abstract: The embodiments of present disclosure provide a thin film transistor, a method for manufacturing the same, and an array substrate. The thin film transistor comprises an active layer provided on a substrate, the active layer including a middle channel region, a first high resistance region and a second high resistance region provided respectively on external sides of the middle channel region, a source region provided on an external side of the first high resistance region and a drain region provided on an external side of the second high resistance region, wherein a base material of the active layer is diamond single crystal. According to the thin film transistor, the method for manufacturing the same, and the array substrate provided in the embodiments of present disclosure, by providing high resistance regions on external sides of the middle channel region of the active layer, the carrier mobility is reduced and the leakage current of the thin film transistor made of single crystalline diamond is effectively suppressed.

公开(公告)号：US10062566B2

公开(公告)日：2018-08-28

申请号：US14894908

申请日：2015-07-16

Applicant: BOE TECHNOLOGY GROUP CO., LTD.

Inventor： Wenqing Xu ,  Chunping Long

IPC: H01L27/14 ,  H01L29/04 ,  H01L27/15 ,  H01L29/18 ,  H01L21/02 ,  H01L29/16 ,  H01L29/786 ,  H01L27/12

CPC classification number: H01L21/02513 ,  H01L21/02488 ,  H01L21/02502 ,  H01L21/02532 ,  H01L21/02592 ,  H01L21/02595 ,  H01L21/02675 ,  H01L27/1218 ,  H01L27/1222 ,  H01L27/1274 ,  H01L27/1277 ,  H01L29/04 ,  H01L29/16 ,  H01L29/78672

Abstract: A semiconductor device, comprising a base substrate, a buffer layer and a polysilicon layer film, wherein the base substrate, the buffer layer and the polysilicon layer film being laminated sequentially, and wherein regularly arranged first grooves being provided on a surface of the buffer layer contacting the polysilicon film; the polysilicon film being formed, by applying crystallization treatment, through an optical annealing process, to an amorphous silicon film on the buffer layer having regularly arranged first grooves.

公开(公告)号：US20180190671A1

公开(公告)日：2018-07-05

申请号：US15552242

申请日：2017-01-09

Applicant: BOE TECHNOLOGY GROUP CO., LTD.

Inventor： Chunping Long ,  Yong Qiao

IPC: H01L27/12 ,  H01L29/786 ,  H01L29/49

CPC classification number: H01L27/124 ,  H01L27/12 ,  H01L27/1222 ,  H01L27/127 ,  H01L29/4908 ,  H01L29/78675 ,  H01L29/78678 ,  H01L29/78696

Abstract: The present disclosure provides a thin film transistor array substrate and a display device implementing the same. The thin film transistor array substrate includes a substrate; a first signal line formed on the substrate; and a thin film transistor formed on the substrate, and an active layer of the thin film transistor and the first signal line are located on different layers above the substrate and projections of them on a plane where the substrate is located overlap with each other at at least two positions. The present disclosure may improve wiring efficiency and reliability of the thin film transistor array substrate.

公开(公告)号：US09786500B2

公开(公告)日：2017-10-10

申请号：US15038350

申请日：2015-12-28

Applicant: BOE TECHNOLOGY GROUP CO., LTD.

Inventor： Wenqing Xu ,  Hongwei Tian ,  Chunping Long

IPC: H01L21/02 ,  H01L29/66 ,  H01L29/786 ,  H01L27/12 ,  C30B1/02 ,  C30B28/02 ,  C30B29/06

CPC classification number: H01L21/02686 ,  C30B1/023 ,  C30B28/02 ,  C30B29/06 ,  H01L21/0245 ,  H01L21/02488 ,  H01L21/02502 ,  H01L21/02532 ,  H01L21/02592 ,  H01L21/0262 ,  H01L27/1222 ,  H01L27/1285 ,  H01L29/6675 ,  H01L29/78603 ,  H01L29/78672 ,  H01L29/78696

Abstract: The present application discloses a method of fabricating a polycrystalline semiconductor layer, comprising forming a heat storage layer; forming a buffer layer on the heat storage layer; forming a first amorphous semiconductor layer on a side of the buffer layer distal to the heat storage layer; and crystallizing the first amorphous semiconductor layer to form a first polycrystalline semiconductor layer.

公开(公告)号：US09761616B2

公开(公告)日：2017-09-12

申请号：US14646925

申请日：2014-10-01

Applicant: BOE Technology Group Co., Ltd.

Inventor： Chunping Long ,  Yinan Liang ,  Lujiang Huangfu

IPC: H01L27/12 ,  H01L21/28 ,  H01L29/66 ,  H01L29/786 ,  H01L21/285 ,  H01L27/32

CPC classification number: H01L27/1288 ,  H01L21/28008 ,  H01L21/28158 ,  H01L21/28506 ,  H01L27/12 ,  H01L27/1262 ,  H01L27/127 ,  H01L27/1274 ,  H01L27/3244 ,  H01L29/66765 ,  H01L29/78678 ,  H01L29/78696 ,  H01L2251/5315

Abstract: An array substrate, a manufacturing method thereof and a display device are disclosed. Patterns comprising a gate, a gate insulating layer and a polysilicon active layer are formed on a base substrate by single patterning process. A passivation layer is formed on the substrate surface formed with the patterns, and patterns of a first via and a second via are formed on a surface of the passivation layer by single patterning process. Patterns of a source, a drain and a pixel electrode are formed on the substrate surface formed with the patterns by single patterning process. The source is electrically connected with the polysilicon active layer through the first via, and the drain is electrically connected with the polysilicon active layer through the second via. A pattern of pixel defining layer is formed on the substrate surface formed with the patterns by single patterning process.

公开(公告)号：US20170170214A1

公开(公告)日：2017-06-15

申请号：US15443028

申请日：2017-02-27

Applicant: BOE Technology Group Co., Ltd.

Inventor： Chunping Long ,  Jang Soon Im ,  Chien Hung Liu

IPC: H01L27/12 ,  H01L21/266 ,  H01L21/265 ,  H01L29/66 ,  H01L29/786

CPC classification number: H01L27/1288 ,  G02F1/134363 ,  G02F1/136227 ,  G02F1/136286 ,  G02F1/1368 ,  G02F2001/136231 ,  G02F2001/13625 ,  H01L21/26513 ,  H01L21/266 ,  H01L21/77 ,  H01L27/12 ,  H01L27/124 ,  H01L27/1248 ,  H01L27/1255 ,  H01L27/1274 ,  H01L27/3248 ,  H01L27/3262 ,  H01L29/41733 ,  H01L29/42384 ,  H01L29/66757 ,  H01L29/78618 ,  H01L29/78675

Abstract: An array substrate, a manufacturing method thereof, a display device, a thin-film transistor (TFT) and a manufacturing method thereof are disclosed. The method for manufacturing the TFT comprises: forming a pattern of an active layer and a gate insulating layer provided with a metal film on a base substrate; patterning the metal film by one patterning process, and forming patterns of a gate electrode, a source electrode, a drain electrode, a gate line and a data line; forming a passivation layer on the base substrate; patterning the passivation layer by one patterning process, and forming a source contact hole, a drain contact hole and a bridge structure contact hole; and forming a transparent conductive film on the base substrate, and removing partial transparent conductive film to form a source contact portion, a drain contact portion (214), a pixel electrode and a bridge structure. The manufacturing method can reduce the number of the patterning processes.

公开(公告)号：US20170103890A1

公开(公告)日：2017-04-13

申请号：US15038350

申请日：2015-12-28

Applicant: BOE TECHNOLOGY GROUP CO., LTD.

Inventor： Wenqing Xu ,  Hongwei Tian ,  Chunping Long

IPC: H01L21/02 ,  H01L29/786 ,  C30B29/06 ,  C30B1/02 ,  C30B28/02 ,  H01L29/66 ,  H01L27/12

CPC classification number: H01L21/02686 ,  C30B1/023 ,  C30B28/02 ,  C30B29/06 ,  H01L21/0245 ,  H01L21/02488 ,  H01L21/02502 ,  H01L21/02532 ,  H01L21/02592 ,  H01L21/0262 ,  H01L27/1222 ,  H01L27/1285 ,  H01L29/6675 ,  H01L29/78603 ,  H01L29/78672 ,  H01L29/78696

Abstract: The present application discloses a method of fabricating a polycrystalline semiconductor layer, comprising forming a heat storage layer; forming a buffer layer on the heat storage layer; forming a first amorphous semiconductor layer on a side of the buffer layer distal to the heat storage layer; and crystallizing the first amorphous semiconductor layer to form a first polycrystalline semiconductor layer.

公开(公告)号：US20160351602A1

公开(公告)日：2016-12-01

申请号：US15232641

申请日：2016-08-09

Applicant: BOE TECHNOLOGY GROUP CO., LTD.

Inventor： Xueyan Tian ,  Chunping Long

IPC: H01L27/12 ,  H01L29/66 ,  H01L29/786 ,  H01L21/02

CPC classification number: H01L27/1281 ,  H01L21/02112 ,  H01L21/02422 ,  H01L21/02488 ,  H01L21/02491 ,  H01L21/02494 ,  H01L21/02502 ,  H01L21/02532 ,  H01L21/02592 ,  H01L21/02672 ,  H01L21/02686 ,  H01L27/1262 ,  H01L29/66757 ,  H01L29/78675

Abstract: A method for producing a low temperature polycrystalline silicon thin film, comprising steps of: providing a substrate; forming a thermal conduction and electrical insulation layer, a buffer layer and an amorphous silicon layer on the substrate in this order; and performing a high-temperature treatment and a laser annealing on the amorphous silicon layer to convert the amorphous silicon layer to a polycrystalline silicon thin film, wherein the thermal conduction and electrical insulation layer comprises regular patterns distributed on the substrate.

Abstract translation: 一种生产低温多晶硅薄膜的方法，包括以下步骤：提供基底; 在该基板上依次形成导热和电绝缘层，缓冲层和非晶硅层; 以及对所述非晶硅层进行高温处理和激光退火以将所述非晶硅层转换为多晶硅薄膜，其中所述导热和电绝缘层包括分布在所述基板上的规则图案。

公开(公告)号：US09478562B2

公开(公告)日：2016-10-25

申请号：US14646416

申请日：2014-09-23

Applicant: BOE TECHNOLOGY GROUP CO., LTD.

Inventor： Chunping Long ,  Zheng Liu ,  Zuqiang Wang ,  Jang Soon Im

IPC: H01L21/00 ,  H01L27/12 ,  H01L29/66 ,  H01L29/786 ,  H01L27/32

CPC classification number: H01L27/1222 ,  H01L21/77 ,  H01L27/12 ,  H01L27/1214 ,  H01L27/1218 ,  H01L27/124 ,  H01L27/1248 ,  H01L27/1255 ,  H01L27/1274 ,  H01L27/1288 ,  H01L27/3246 ,  H01L27/3248 ,  H01L27/3262 ,  H01L27/3265 ,  H01L29/66757 ,  H01L29/78675 ,  H01L2227/323

Abstract: An array substrate and manufacturing method thereof, a display device, a thin film transistor and manufacturing method thereof are provided. The manufacturing method of an array substrate includes forming an active material layer (501), a gate insulating layer (204) and a metal thin film (502) on a base substrate (201), and forming a pattern including an active layer (203) and a pattern including a gate electrode (205), a source electrode (206), a drain electrode (207), a gate line (1063) and a data line (1061) by a first patterning process; forming a passivation layer (301) on the base substrate (201), and forming a source contact hole (302), a drain contact hole (303), and an bridge-structure contact hole (1062a) by a second patterning process; forming a transparent conductive thin film (1401) on the base substrate (201), and removing the transparent conductive thin film (1404) partially, so that a source contact section (401), a drain contact section (402), a pixel electrode (403), and an bridge structure (1062) are formed. With the manufacturing method, the use number of patterning processes is decreased.

Abstract translation: 提供阵列基板及其制造方法，显示装置，薄膜​​晶体管及其制造方法。 阵列基板的制造方法包括在基底基板（201）上形成活性物质层（501），栅极绝缘层（204）和金属薄膜（502），形成包括活性层（203）的图案 ）和通过第一图案化工艺包括栅电极（205），源电极（206），漏电极（207），栅线（1063）和数据线（1061）的图案; 在所述基底基板上形成钝化层，通过第二构图工艺形成源极接触孔，漏极接触孔和桥接结构接触孔; 在所述基底基板上形成透明导电薄膜，将所述透明导电薄膜部分地去除，使得源极接触部分，漏极接触部分，像素电极， （403）和桥结构（1062）。 通过制造方法，图案化处理的使用次数减少。