公开(公告)号：US10388652B2

公开(公告)日：2019-08-20

申请号：US15811961

申请日：2017-11-14

Applicant: GLOBALFOUNDRIES INC.

Inventor： Yongiun Shi ,  Lei Sun ,  Laertis Economikos ,  Ruilong Xie ,  Lars Liebmann ,  Chanro Park ,  Daniel Chanemougame ,  Min Gyu Sung ,  Hsien-Ching Lo ,  Haiting Wang

IPC: H01L27/088 ,  H01L21/311 ,  H01L21/8234 ,  H01L29/66 ,  H01L29/06 ,  H01L27/02 ,  H01L21/762 ,  H01L21/308 ,  H01L21/3105 ,  H01L21/027

Abstract: The disclosure provides integrated circuit (IC) structures with single diffusion break (SDB) abutting end isolation regions, and methods of forming the same. An IC structure may include: a plurality of fins positioned on a substrate; a plurality of gate structures each positioned on the plurality of fins and extending transversely across the plurality of fins; an insulator region positioned on the plurality of fins and laterally between the plurality of gate structures; at least one single diffusion break (SDB) positioned within the insulator region and one of the plurality of fins, the at least one SDB region extending from an upper surface of the substrate to an upper surface of the insulator region; and an end isolation region abutting a lateral end of the at least one SDB along a length of the plurality of gate structures, the end isolation region extending substantially in parallel with the plurality of fins.

公开(公告)号：US20190252267A1

公开(公告)日：2019-08-15

申请号：US16390232

申请日：2019-04-22

Applicant: GLOBALFOUNDRIES INC.

Inventor： Ruilong Xie ,  Steven Bentley ,  Puneet Harischandra Suvarna ,  Chanro Park ,  Min Gyu Sung ,  Lars Liebmann ,  Su Chen Fan ,  Brent Anderson

IPC: H01L21/8238 ,  H01L29/66 ,  H01L29/78 ,  H01L21/84 ,  H01L29/06 ,  H01L21/8234

CPC classification number: H01L21/823821 ,  H01L21/823431 ,  H01L21/845 ,  H01L29/0653 ,  H01L29/6656 ,  H01L29/66583 ,  H01L29/66636 ,  H01L29/66795 ,  H01L29/7848 ,  H01L29/78642

Abstract: A vertical FinFET includes a semiconductor fin formed over a semiconductor substrate. A self-aligned first source/drain contact is electrically separated from a second source/drain contact by a sidewall spacer that is formed over an endwall of the fin. The sidewall spacer, which comprises a dielectric material, allows the self-aligned first source/drain contact to be located in close proximity to an endwall of the fin and the associated second source/drain contact without risk of an electrical short between the adjacent contacts.

公开(公告)号：US20190198381A1

公开(公告)日：2019-06-27

申请号：US16288780

申请日：2019-02-28

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Chanro Park ,  Min Gyu Sung ,  Hoon Kim ,  Ruilong Xie

IPC: H01L21/768 ,  H01L29/66

CPC classification number: H01L21/7682 ,  H01L29/6653 ,  H01L29/66545 ,  H01L29/66795

Abstract: Structures for air-gap spacers in a field-effect transistor and methods for forming air-gap spacers in a field-effect transistor. A gate structure is formed on a top surface of a semiconductor body. A dielectric spacer is formed adjacent to a vertical sidewall of the gate structure. A semiconductor layer is formed on the top surface of the semiconductor body. The semiconductor layer is arranged relative to the vertical sidewall of the gate structure such that a first section of the first dielectric spacer is located in a space between the semiconductor layer and the vertical sidewall of the gate structure. A second section of the dielectric spacer that is located above a top surface of the semiconductor layer is removed. An air-gap spacer is formed in a space from which the second section of the dielectric spacer is removed.

公开(公告)号：US10290549B2

公开(公告)日：2019-05-14

申请号：US15695229

申请日：2017-09-05

Applicant: GLOBALFOUNDRIES INC.

Inventor： Ruilong Xie ,  Julien Frougier ,  Min Gyu Sung ,  Edward Joseph Nowak ,  Nigel G. Cave ,  Lars Liebmann ,  Daniel Chanemougame ,  Andreas Knorr

IPC: H01L21/8238 ,  H01L27/092 ,  H01L29/06 ,  H01L29/423 ,  H01L29/786 ,  H01L29/66 ,  H01L27/11

Abstract: The disclosure is directed to gate all-around integrated circuit structures, finFETs having a dielectric isolation, and methods of forming the same. The gate all-around integrated circuit structure may include a first insulator region within a substrate; a pair of remnant liner stubs disposed within the first insulator region; a second insulator region laterally adjacent to the first insulator region within the substrate; a pair of fins over the first insulator region, each fin in the pair of fins including an inner sidewall facing the inner sidewall of an adjacent fin in the pair of fins and an outer sidewall opposite the inner sidewall; and a gate structure substantially surrounding an axial portion of the pair of fins and at least partially disposed over the first and second insulator regions, wherein each remnant liner stub is substantially aligned with the inner sidewall of a respective fin of the pair of fins.

公开(公告)号：US20190096679A1

公开(公告)日：2019-03-28

申请号：US15712996

申请日：2017-09-22

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Balaji Kannan ,  Bala Haran ,  Vimal K. Kamineni ,  Sungkee Han ,  Neal Makela ,  Suraj K. Patil ,  Pei Liu ,  Chih-Chiang Chang ,  Katsunori Onishi ,  Keith Kwong Hon Wong ,  Ruilong Xie ,  Chanro Park ,  Min Gyu Sung

IPC: H01L21/28 ,  H01L29/423 ,  H01L29/49 ,  H01L29/78

Abstract: Structures for a field-effect transistor and methods for forming a structure for a field-effect transistor. A gate cavity is formed in a dielectric layer that includes a bottom surface and a plurality sidewalls that extend to the bottom surface. A gate dielectric layer is formed at the sidewalls and the bottom surface of the gate cavity. A work function metal layer is deposited on the gate dielectric layer at the sidewalls and the bottom surface of the gate cavity. A fill metal layer is deposited inside the gate cavity after the work function metal layer is deposited. The fill metal layer is formed in direct contact with the work function metal layer.

公开(公告)号：US10177041B2

公开(公告)日：2019-01-08

申请号：US15455203

申请日：2017-03-10

Applicant: GLOBALFOUNDRIES INC.

Inventor： Ruilong Xie ,  Laertis Economikos ,  Chanro Park ,  Min Gyu Sung

IPC: H01L21/8238 ,  H01L21/324 ,  H01L29/66 ,  H01L27/092 ,  H01L29/78

Abstract: Disclosed are method embodiments for forming an integrated circuit (IC) structure with at least one first-type FINFET and at least one second-type FINFET, wherein the first-type FINFET has a first replacement metal gate (RMG) adjacent to a first semiconductor fin, the second-type FINFET has a second RMG adjacent to a second semiconductor fin, and the first RMG is in end-to-end alignment with the second RMG and physically and electrically isolated from the second RMG by a dielectric column. The method embodiments minimize the risk of the occurrence defects within the RMGs by forming the dielectric column during formation of the first and second RMGs and, particularly, after deposition and anneal of a gate dielectric layer for the first and second RMGs, but before deposition of at least one of multiple work function metal layers. Also disclosed herein are IC structure embodiments formed according to the above-described method embodiments.

公开(公告)号：US10170544B2

公开(公告)日：2019-01-01

申请号：US15833285

申请日：2017-12-06

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Ruilong Xie ,  Christopher M. Prindle ,  Min Gyu Sung ,  Tek Po Rinus Lee

IPC: H01L29/06 ,  H01L21/311 ,  H01L21/762 ,  H01L29/66 ,  H01L29/78

Abstract: An integrated circuit product includes a FinFET device, a device isolation region that is positioned around a perimeter of the FinFET device, and an isolation protection layer that is positioned above the device isolation region. The FinFET device includes at least one fin, a gate structure, and a sidewall spacer, the device isolation region includes a first insulating material, and the isolation protection layer includes a material that is different from the first insulating material. A first portion of the isolation protection layer is positioned under a portion of the gate structure and under a portion of the sidewall spacer, wherein a second portion of the isolation protection layer is not positioned under the gate structure and is not positioned under the sidewall spacer, the first portion of the isolation protection layer having a thickness that is greater than a thickness of the second portion.

公开(公告)号：US10121702B1

公开(公告)日：2018-11-06

申请号：US15638087

申请日：2017-06-29

Applicant: GLOBALFOUNDRIES INC.

Inventor： Chanro Park ,  Min Gyu Sung ,  Ruilong Xie ,  Puneet H. Suvarna

IPC: H01L21/768 ,  H01L29/66 ,  H01L21/8234 ,  H01L27/088 ,  H01L29/08 ,  H01L23/535

Abstract: At least one method, apparatus and system disclosed herein involves performing an early-process of source/drain (S/D) contact cut and S/D contact etch steps for manufacturing a finFET device. A gate structure, a source structure, and a drain structure of a transistor are formed. The gate structure comprises a dummy gate region, a gate spacer, and a liner. A source/drain (S/D) contact cut process is performed. An S/D contact etch process is performed. A replacement metal gate (RMG) process is performed subsequent to performing the S/D contact etch process. An S/D contact metallization process is performed.

公开(公告)号：US10084053B1

公开(公告)日：2018-09-25

申请号：US15470205

申请日：2017-03-27

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Ruilong Xie ,  Chanro Park ,  Min Gyu Sung

IPC: H01L21/82 ,  H01L29/423 ,  H01L21/8234 ,  H01L21/28 ,  H01L29/417

Abstract: Structures involving a field-effect transistor and methods for forming a structure that involves a field-effect transistor. A first metal gate electrode and a second metal gate electrode are formed that are embedded in a first dielectric layer. A second dielectric layer is formed on the first metal gate electrode, the second metal gate electrode, and the first dielectric layer. An opening is formed in the second dielectric layer that extends in a vertical direction to expose a section of the first metal gate electrode. The section of the first metal gate electrode is removed, while the second metal gate electrode is masked by the second dielectric layer, to define a gate cut at a location of the opening. The gate cut may be subsequently filled by dielectric material.

公开(公告)号：US20180122919A1

公开(公告)日：2018-05-03

申请号：US15337254

申请日：2016-10-28

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Chanro Park ,  Ruilong Xie ,  Hoon Kim ,  Min Gyu Sung

IPC: H01L29/66 ,  H01L29/40 ,  H01L21/28 ,  H01L21/3213

CPC classification number: H01L29/66545 ,  H01L21/28026 ,  H01L21/3213 ,  H01L29/401 ,  H01L29/66568 ,  H01L29/66636 ,  H01L29/66795

Abstract: One illustrative method disclosed includes, among other things, removing a portion of an initial gate cap layer and a portion of an initial sidewall spacer so as to thereby define a gate contact cavity that exposes a portion of a gate structure, completely forming a conductive gate contact structure (CB) in a gate contact cavity, wherein the entire conductive gate contact structure (CB) is positioned vertically above the active region. The method also comprises removing the remaining portion of the initial gate cap layer and to recess a vertical height of exposed portions of the initial sidewall spacer to thereby define a recessed sidewall spacer and a gate cap cavity and forming a replacement gate cap layer in the gate cap cavity so as to define an air space between an upper surface of the recessed sidewall spacer and a lower surface of the replacement gate cap layer.