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    METHODS OF REMOVING GATE CAP LAYERS IN CMOS APPLICATIONS
    111.
    发明申请
    METHODS OF REMOVING GATE CAP LAYERS IN CMOS APPLICATIONS 有权
    CMOS应用中去除盖子层的方法

    公开(公告)号：US20140256135A1

    公开(公告)日：2014-09-11

    申请号：US13792540

    申请日：2013-03-11

    Applicant: GLOBALFOUNDRIES INC.

    Inventor： Peter Javorka ,  Ralf Richter ,  Stefan Flachowsky ,  Jan Hoentschel

    IPC: H01L21/308

    CPC classification number: H01L21/823807 ,  H01L21/823814 ,  H01L21/823828 ,  H01L21/823864 ,  H01L29/6653 ,  H01L29/66545

    Abstract: One illustrative method disclosed herein includes the steps of forming a masking layer that covers a P-type transistor and exposes at least a gate cap layer of an N-type transistor, performing a first etching process through the masking layer to remove a portion of the gate cap of the N-type transistor so as to thereby define a reduced thickness gate cap layer for the N-type transistor, removing the masking layer, and performing a common second etching process on the P-type transistor and the N-type transistor that removes a gate cap layer of the P-type transistor and the reduced thickness gate cap of the N-type transistor.

    Abstract translation: 本文公开的一种说明性方法包括以下步骤：形成覆盖P型晶体管并暴露N型晶体管的至少栅极帽层的掩模层，通过掩模层执行第一蚀刻工艺以去除部分 N型晶体管的栅极帽，从而限定了用于N型晶体管的减小厚度的栅极盖层，去除掩模层，并对P型晶体管和N型晶体管执行公共的第二蚀刻工艺 其去除了N型晶体管的P型晶体管的栅极盖层和减小厚度的栅极盖。

    CONTACT GEOMETRY HAVING A GATE SILICON LENGTH DECOUPLED FROM A TRANSISTOR LENGTH
    112.
    发明申请
    CONTACT GEOMETRY HAVING A GATE SILICON LENGTH DECOUPLED FROM A TRANSISTOR LENGTH 有权
    联系几何具有从晶体管长度去除的栅极长度

    公开(公告)号：US20140252429A1

    公开(公告)日：2014-09-11

    申请号：US13792730

    申请日：2013-03-11

    Applicant: GLOBALFOUNDRIES INC.

    Inventor： Ralf Richter ,  Peter Javorka ,  Jan Hoentschel ,  Stefan Flachowsky

    IPC: H01L29/78 ,  H01L21/28 ,  H01L29/66

    CPC classification number: H01L29/42376 ,  H01L21/28008 ,  H01L21/28052 ,  H01L21/28114 ,  H01L21/28123 ,  H01L29/4933 ,  H01L29/4966 ,  H01L29/513 ,  H01L29/517 ,  H01L29/66477 ,  H01L29/665 ,  H01L29/6653 ,  H01L29/66575 ,  H01L29/78

    Abstract: Methods for forming a semiconductor device are provided. In one embodiment, a gate structure having a gate insulating layer and a gate electrode structure formed on the gate insulating layer is provided. The methods provide reducing a dimension of the gate electrode structure relative to the gate insulating layer along a direction extending in parallel to a direction connecting the source and drain. A semiconductor device structure having a gate structure including a gate insulating layer and a gate electrode structure formed above the gate insulating layer is provided, wherein a dimension of the gate electrode structure extending along a direction which is substantially parallel to a direction being oriented from source to drain is reduced relative to a dimension of the gate insulating layer. According to some examples, gate structures are provided having a gate silicon length which is decoupled from the channel width induced by the gate structure.

    Abstract translation: 提供了形成半导体器件的方法。 在一个实施例中，提供了一种在栅极绝缘层上形成栅极绝缘层和栅电极结构的栅极结构。 所述方法提供了沿着平行于连接源极和漏极的方向延伸的方向，相对于栅极绝缘层减小栅电极结构的尺寸。 提供一种具有栅极结构的半导体器件结构，该栅极结构包括形成在栅极绝缘层上方的栅极绝缘层和栅电极结构，其中栅电极结构的尺寸沿着基本上平行于源极方向的方向延伸 漏极相对于栅极绝缘层的尺寸减小。 根据一些示例，提供具有栅极硅长度的栅极结构，其与由栅极结构引起的沟道宽度解耦。

    STRESS MEMORIZATION TECHNIQUE
    113.
    发明申请
    STRESS MEMORIZATION TECHNIQUE 审中-公开
    应力记忆技术

    公开(公告)号：US20140248749A1

    公开(公告)日：2014-09-04

    申请号：US13783685

    申请日：2013-03-04

    Applicant: GLOBALFOUNDRIES INC.

    Inventor： Jan Hoentschel ,  Stefan Flachowsky ,  Nicolas Sassiat ,  Ralf Richter

    IPC: H01L21/8238 ,  H01L29/66

    CPC classification number: H01L21/823814 ,  H01L21/823807 ,  H01L21/823864 ,  H01L29/665 ,  H01L29/66575 ,  H01L29/7833 ,  H01L29/7847

    Abstract: A method comprises providing a semiconductor structure comprising a gate structure provided over a semiconductor region. An ion implantation process is performed. In the ion implantation process, a first portion of the semiconductor region adjacent the gate structure and a second portion of the semiconductor region adjacent the gate structure are amorphized so that a first amorphized region and a second amorphized region are formed adjacent the gate structure. An atomic layer deposition process is performed. The atomic layer deposition process deposits a layer of a material having an intrinsic stress over the semiconductor structure. A temperature at which at least a part of the atomic layer deposition process is performed and a duration of the at least a part of the atomic layer deposition process are selected such that the first amorphized region and the second amorphized region are re-crystallized during the atomic layer deposition process.

    Abstract translation: 一种方法包括提供包括设置在半导体区域上的栅极结构的半导体结构。 进行离子注入工艺。 在离子注入工艺中，与栅极结构相邻的半导体区域的第一部分和与栅极结构相邻的半导体区域的第二部分是非晶化的，从而在栅极结构附近形成第一非晶化区域和第二非晶化区域。 进行原子层沉积工艺。 原子层沉积工艺在半导体结构上沉积具有固有应力的材料层。 进行原子层沉积工艺的至少一部分的温度，并且选择原子层沉积工艺的至少一部分的持续时间，使得第一非晶化区域和第二非晶化区域在 原子层沉积工艺。

    Method of forming a semiconductor structure including an implantation of ions into a layer of spacer material
    114.
    发明授权
    Method of forming a semiconductor structure including an implantation of ions into a layer of spacer material 有权
    形成半导体结构的方法，包括将离子注入到间隔物材料层中

    公开(公告)号：US08815741B1

    公开(公告)日：2014-08-26

    申请号：US13793082

    申请日：2013-03-11

    Applicant: GLOBALFOUNDRIES Inc.

    Inventor： Ralf Richter ,  Jan Hoentschel ,  Sven Beyer ,  Peter Javorka

    IPC: H01L21/311 ,  H01L21/265

    CPC classification number: H01L21/265 ,  H01L21/0217 ,  H01L21/02274 ,  H01L21/31155 ,  H01L21/823807 ,  H01L21/823864 ,  H01L29/7843

    Abstract: A method includes providing a semiconductor structure including a substrate and a transistor element. A layer of a spacer material is deposited over the substrate and the gate structure, wherein the deposited layer of spacer material has an intrinsic stress. Ions are implanted into the layer of spacer material. After the deposition of the layer of spacer material and the implantation of ions into the layer of spacer material, a sidewall spacer is formed at sidewalls of the gate structure from the layer of spacer material.

    Abstract translation: 一种方法包括提供包括衬底和晶体管元件的半导体结构。 在衬底和栅极结构上沉积间隔材料层，其中间隔物材料的沉积层具有固有应力。 离子被植入到间隔物材料层中。 在间隔物材料层沉积并将离子注入到间隔物材料层中之后，在间隔物材料层的栅极结构的侧壁处形成侧壁间隔物。

    Communicating optical signals between stacked dies
    117.
    发明授权
    Communicating optical signals between stacked dies 有权

    公开(公告)号：US10283490B2

    公开(公告)日：2019-05-07

    申请号：US15713064

    申请日：2017-09-22

    Applicant: GLOBALFOUNDRIES Inc.

    Inventor： Sven Beyer ,  Jan Hoentschel ,  Alexander Ebermann

    IPC: H01L25/16 ,  H01L23/48 ,  H01L23/00 ,  H01L21/768 ,  H01L25/04

    Abstract: A method includes forming a stack of semiconductor die. The stack includes a first semiconductor die, a second semiconductor die and a third semiconductor die. The first semiconductor die is stacked above the second semiconductor die and the third semiconductor die is stacked above the first semiconductor die. A first optical transmitter and a first optical receiver are provided in the first semiconductor die, a second optical transmitter is provided in the second semiconductor die, and a second optical receiver is provided in the third semiconductor die. A first optical signal is transmitted from the first optical transmitter in the first semiconductor die to the second optical receiver in the third semiconductor die. A second optical signal is transmitted from the second optical transmitter in the second semiconductor die to the first optical receiver in the first semiconductor die.

    Methods for forming integrated circuits that include a dummy gate structure
    118.
    发明授权
    Methods for forming integrated circuits that include a dummy gate structure 有权

    公开(公告)号：US10157996B2

    公开(公告)日：2018-12-18

    申请号：US15648889

    申请日：2017-07-13

    Applicant: GLOBALFOUNDRIES Inc.

    Inventor： Elliot John Smith ,  Jan Hoentschel ,  Nigel Chan ,  Sven Beyer

    IPC: H01L29/49 ,  H01L29/66 ,  H01L21/306 ,  H01L21/308 ,  H01L21/84 ,  H01L27/12 ,  H01L29/06 ,  H01L29/417 ,  H01L29/423 ,  H01L29/78

    Abstract: A method includes forming a first material stack above a first transistor region, a second transistor region, and a dummy gate region of a semiconductor structure, the first material stack including a high-k material layer and a workfunction adjustment metal layer. The first material stack is patterned to remove a first portion of the first material stack from above the dummy gate region while leaving second portions of the first material stack above the first and second transistor regions. A gate electrode stack is formed above the first and second transistor regions and above the dummy gate region, and the gate electrode stack and the remaining second portions of the first material stack are patterned to form a first gate structure above the first transistor region, a second gate structure above the second transistor region, and a dummy gate structure above the dummy gate region.

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