公开(公告)号：US20200161433A1

公开(公告)日：2020-05-21

申请号：US16354973

申请日：2019-03-15

Applicant: Infineon Technologies AG

Inventor： Caspar Leendertz ,  Romain Esteve ,  Anton Mauder ,  Andreas Meiser ,  Bernd Zippelius

IPC: H01L29/16 ,  H01L29/78 ,  H01L29/10 ,  H01L29/08 ,  H01L29/423 ,  H01L29/66

Abstract: Embodiments of SiC devices and corresponding methods of manufacture are provided. In some embodiments, the SiC device has shielding regions at the bottom of some gate trenches and non-linear junctions formed with the SiC material at the bottom of other gate trenches. In other embodiments, the SiC device has the shielding regions at the bottom of the gate trenches and arranged in rows which run in a direction transverse to a lengthwise extension of the trenches. In still other embodiments, the SiC device has the shielding regions and the non-linear junctions, and wherein the shielding regions are arranged in rows which run in a direction transverse to a lengthwise extension of the trenches.

公开(公告)号：US10566426B2

公开(公告)日：2020-02-18

申请号：US15848707

申请日：2017-12-20

Applicant: Infineon Technologies AG

Inventor： Anton Mauder ,  Oliver Hellmund ,  Peter Irsigler ,  Jens Peter Konrath ,  David Laforet ,  Maik Langner ,  Markus Neuber ,  Hans-Joachim Schulze ,  Ralf Siemieniec ,  Knut Stahrenberg ,  Olaf Storbeck

IPC: H01L21/02 ,  H01L29/16 ,  H01L21/28 ,  H01L29/51

Abstract: A body structure and a drift zone are formed in a semiconductor layer, wherein the body structure and the drift zone form a first pn junction. A silicon nitride layer is formed on the semiconductor layer. A silicon oxide layer is formed from at least a vertical section of the silicon nitride layer by oxygen radical oxidation.

公开(公告)号：US20190371794A1

公开(公告)日：2019-12-05

申请号：US16507152

申请日：2019-07-10

Applicant: Infineon Technologies AG

Inventor： Anton Mauder ,  Franz-Josef Niedernostheide ,  Christian Philipp Sandow

IPC: H01L27/088 ,  H01L29/06 ,  H01L29/739 ,  H03K17/687 ,  H01L29/423 ,  H01L29/10 ,  H01L29/78

Abstract: A power semiconductor device includes a semiconductor body coupled to first and second load terminal structures, and first and second cells each configured for controlling a load current and electrically connected to the first load terminal structure and to a drift region. A first mesa in the first cell includes a port region electrically connected to the first load terminal structure, and a first channel region coupled to the drift region. A second mesa included in the second cell includes a port region electrically connected to the first load terminal structure, and a second channel region coupled to the drift region. The mesas are spatially confined in a direction perpendicular to a direction of the load current by an insulation structure, and have a total extension of less than 100 nm in that direction. The first channel region includes an inversion channel. The second channel region includes an accumulation channel.

公开(公告)号：US10453918B2

公开(公告)日：2019-10-22

申请号：US16189858

申请日：2018-11-13

Applicant: Infineon Technologies AG

Inventor： Anton Mauder ,  Franz-Josef Niedernostheide ,  Christian Philipp Sandow

IPC: H01L29/06 ,  H01L29/10 ,  H01L29/40 ,  H01L29/423 ,  H01L29/739 ,  H01L29/78 ,  H01L29/36 ,  H01L29/417

Abstract: A power semiconductor device includes a semiconductor body coupled to first and second load terminal structures, first and second cells electrically connected to the first load terminal structure and to a drift region, the drift region having a first conductivity type; a first mesa in the first cell and including: a port region electrically connected to the first load terminal structure, and a channel region coupled to the drift region; a second mesa in the second cell and including: a port region of the opposite conductivity type and electrically connected to the first load terminal structure, and a channel region coupled to the drift region. Each mesa is spatially confined, in a direction perpendicular to a direction of the load current within the respective mesa, by an insulation structure. The insulation structure houses a control electrode structure, and a guidance electrode arranged between the mesas.

公开(公告)号：US20190267447A1

公开(公告)日：2019-08-29

申请号：US16410293

申请日：2019-05-13

Applicant: Infineon Technologies AG

Inventor： Anton Mauder ,  Franz-Josef Niedernostheide ,  Christian Philipp Sandow

IPC: H01L29/06 ,  H01L29/739 ,  H01L29/78

Abstract: A power semiconductor device includes a semiconductor body coupled to first and second load terminal structures, an active cell field in the body, and a plurality of first and second cells in the active cell field. Each cell is electrically connected to the first load terminal structure and to a drift region. Each first cell includes a mesa having a port region electrically connected to the first load terminal structure, and a channel region coupled to the drift region. Each second cell includes a mesa having a port region of the opposite conductivity type electrically connected to the first load terminal structure, and a channel region coupled to the drift region. Each mesa is spatially confined in a direction perpendicular to a direction of the load current within the respective mesa, by an insulation structure and has a total extension of less than 100 nm in the direction.

公开(公告)号：US20190109188A1

公开(公告)日：2019-04-11

申请号：US16196373

申请日：2018-11-20

Applicant: Infineon Technologies AG

Inventor： Anton Mauder ,  Franz-Josef Niedernostheide ,  Frank Dieter Pfirsch ,  Christian Philipp Sandow

IPC: H01L29/06 ,  H03K17/567 ,  H01L29/10 ,  H01L29/739 ,  H01L29/08 ,  H01L29/40 ,  H01L29/78

CPC classification number: H01L29/063 ,  H01L29/0634 ,  H01L29/0696 ,  H01L29/0834 ,  H01L29/1095 ,  H01L29/407 ,  H01L29/7394 ,  H01L29/7397 ,  H01L29/7803 ,  H01L29/7804 ,  H01L29/7813 ,  H01L29/7828 ,  H03K17/567

Abstract: A power semiconductor device is disclosed. The device includes a semiconductor body coupled to a first load terminal structure and a second load terminal structure, a first cell and a second cell. A first mesa is included in the first cell, the first mesa including: a first port region and a first channel region. A second mesa included in the second cell, the second mesa including a second port region. A third cell is electrically connected to the second load terminal structure and electrically connected to a drift region. The third cell includes a third mesa comprising: a third port region, a third channel region, and a third control electrode.

公开(公告)号：US10153764B2

公开(公告)日：2018-12-11

申请号：US15377750

申请日：2016-12-13

Applicant: Infineon Technologies AG

Inventor： Markus Bina ,  Jens Barrenscheen ,  Anton Mauder

IPC: H03K3/00 ,  H03K17/56 ,  G01R19/00 ,  H01L49/02 ,  H01L29/68

Abstract: A semiconductor device includes a first load terminal, a second load terminal and a semiconductor body coupled to the first load terminal and the second load terminal. The semiconductor body is configured to conduct a load current along a load current path between the first load terminal and the second load terminal. The semiconductor device further includes a control electrode electrically insulated from the semiconductor body and configured to control a part of the load current path, and an electrically floating sensor electrode arranged adjacent to the control electrode. The sensor electrode is electrically insulated from each of the semiconductor body, and the control electrode and is capacitively coupled to the load current path.

公开(公告)号：US09954065B2

公开(公告)日：2018-04-24

申请号：US14936279

申请日：2015-11-09

Applicant: Infineon Technologies AG

Inventor： Anton Mauder ,  Frank Pfirsch ,  Hans-Joachim Schulze ,  Ingo Muri ,  Iris Moder ,  Johannes Baumgartl

IPC: H01L29/10 ,  H01L21/265 ,  H01L21/324 ,  H01L21/304 ,  H01L21/306 ,  H01L21/3205 ,  H01L27/088 ,  H01L29/66 ,  H01L29/78 ,  H01L29/417 ,  H01L29/45 ,  H01L29/739 ,  H01L29/06 ,  H01L29/08

CPC classification number: H01L29/1095 ,  H01L21/265 ,  H01L21/304 ,  H01L21/30604 ,  H01L21/30608 ,  H01L21/3065 ,  H01L21/3083 ,  H01L21/3205 ,  H01L21/324 ,  H01L27/088 ,  H01L29/0661 ,  H01L29/0834 ,  H01L29/16 ,  H01L29/1608 ,  H01L29/2003 ,  H01L29/417 ,  H01L29/45 ,  H01L29/66136 ,  H01L29/66348 ,  H01L29/66477 ,  H01L29/7397 ,  H01L29/78

Abstract: In accordance with a method of forming a semiconductor device, an auxiliary structure is formed at a first surface of a silicon semiconductor body. A semiconductor layer is formed on the semiconductor body at the first surface. Semiconductor device elements are formed at the first surface. The semiconductor body is then removed from a second surface opposite to the first surface at least up to an edge of the auxiliary structure oriented to the second surface.

公开(公告)号：US09923066B2

公开(公告)日：2018-03-20

申请号：US15221122

申请日：2016-07-27

Applicant: Infineon Technologies AG

Inventor： Daniel Kueck ,  Thomas Aichinger ,  Franz Hirler ,  Anton Mauder

IPC: H01L29/40 ,  H01L29/78 ,  H01L29/739 ,  H01L29/10 ,  H01L29/423 ,  H01L29/06 ,  H01L29/16 ,  H01L29/20

CPC classification number: H01L29/408 ,  H01L29/0619 ,  H01L29/1095 ,  H01L29/1608 ,  H01L29/2003 ,  H01L29/407 ,  H01L29/42368 ,  H01L29/7397 ,  H01L29/7811 ,  H01L29/7813

Abstract: A semiconductor device includes a source zone electrically connected to a first load terminal, a contiguous zone isolating the source zone from a drift zone, and a trench extending into a semiconductor body along a vertical direction and including a first electrode electrically connected to a control terminal and an insulator in contact with the contiguous zone and which isolates the first electrode from the semiconductor body. The insulator has, at a trench bottom region, a first thickness along the vertical direction, and, at a trench top region, a second thickness along a lateral direction, the first thickness being greater than the second thickness by a factor of at least 1.5. The contiguous zone is arranged in contact with the insulator and extends further along the vertical direction than the trench, and the trench bottom region and the contiguous zone overlap along the lateral direction.

公开(公告)号：US20180061962A1

公开(公告)日：2018-03-01

申请号：US15724604

申请日：2017-10-04

Applicant: Infineon Technologies AG

Inventor： Hans-Joachim Schulze ,  Franz Hirler ,  Anton Mauder ,  Helmut Strack ,  Frank Kahlmann ,  Gerhard Miller

IPC: H01L29/66 ,  H01L29/872 ,  H01L29/861 ,  H01L21/265 ,  H01L29/08 ,  H01L29/10 ,  H01L29/167 ,  H01L29/36 ,  H01L29/739 ,  H01L29/78 ,  H01L29/74 ,  H01L29/40 ,  H01L29/06 ,  H01L29/165 ,  H01L21/22

CPC classification number: H01L29/66348 ,  H01L21/2205 ,  H01L21/2658 ,  H01L29/0619 ,  H01L29/0634 ,  H01L29/0638 ,  H01L29/0878 ,  H01L29/102 ,  H01L29/1095 ,  H01L29/165 ,  H01L29/167 ,  H01L29/36 ,  H01L29/402 ,  H01L29/404 ,  H01L29/407 ,  H01L29/7397 ,  H01L29/7428 ,  H01L29/7802 ,  H01L29/7811 ,  H01L29/7813 ,  H01L29/7816 ,  H01L29/861 ,  H01L29/872

Abstract: A semiconductor device is produced by providing a semiconductor substrate, forming an epitaxial layer on the semiconductor substrate, and introducing dopant atoms of a first doping type and dopant atoms of a second doping type into the epitaxial layer.