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公开(公告)号：US09628061B2
公开(公告)日：2017-04-18
申请号：US14860761
申请日：2015-09-22
Applicant: Macronix International Co., Ltd.
Inventor： Kuan-Ming Lu , Chun-Hsiung Hung , Chun-Yi Lee , Ken-Hui Chen , Kuen-Long Chang
IPC: H03K5/153 , H03K5/1534
CPC classification number: H03K5/1534
Abstract: A power drop detector circuit includes a detect element, for coupling to a first source voltage, for detecting a voltage level of the first source voltage, and a memory element coupled to the detect element and switchable between a first memory state and a second memory state based on the voltage level of the first source voltage.
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112.发明授权Page buffer circuit having bias voltage application unit and operating method of same 有权具有偏置电压施加单元的页缓冲电路及其操作方法公开(公告)号：US09589646B2
公开(公告)日：2017-03-07
申请号：US14554293
申请日：2014-11-26
Applicant: MACRONIX INTERNATIONAL CO., LTD.
Inventor： Chung-Kuang Chen , Han-Sung Chen , Chun-Hsiung Hung
CPC classification number: G11C16/10 , G06F3/0619 , G06F3/0656 , G06F3/0679 , G11C7/02 , G11C16/0483
Abstract: A page buffer circuit includes a plurality of page buffers including a first page buffer. The first page buffer is configured to load input data of the first page buffer, and input data of at least one neighboring page buffer. The first page buffer is also configured to apply a bias corresponding to the input data of the first page buffer, and the input data of the at least one neighboring page buffer to a bit line.
Abstract translation: 页面缓冲电路包括多个页缓冲器，包括第一页缓冲器。 第一页缓冲器被配置为加载第一页缓冲器的输入数据，并输入至少一个相邻页缓冲器的数据。 第一页缓冲器还被配置为将与第一页缓冲器的输入数据相对应的偏置以及至少一个相邻页缓冲器的输入数据施加到位线。
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公开(公告)号：US09535785B2
公开(公告)日：2017-01-03
申请号：US14158613
申请日：2014-01-17
Applicant: Macronix International Co., Ltd.
Inventor： Nai-Ping Kuo , Shih-Chang Huang , Chin-Hung Chang , Ken-Hui Chen , Kuen-Long Chang , Chun-Hsiung Hung
CPC classification number: G06F11/1048 , G06F2212/1036 , G11C16/3436
Abstract: A method of operating a memory storing data sets, and ECCs for the data sets is provided. The method includes when writing new data in a data set, computing and storing an ECC, if a number of addressable segments storing the new data and data previously programmed in the data set includes at least a predetermined number of addressable segments. The method includes storing indications for whether to enable or disable use of the ECCs, using the ECC and a first additional ECC bit derived from the ECC. The method includes reading from a data set an extended ECC including an ECC and a first additional ECC bit derived from the ECC, and enabling or disabling use of the ECC according to the indications stored for the data set. The method includes enabling use of ECCs for blank data sets, using the indications and a second additional ECC bit.
Abstract translation: 提供了一种操作存储数据集的存储器和数据集的ECC的方法。 如果存储新数据的多个可寻址段和先前在数据集中编程的数据包括至少预定数量的可寻址段，则该方法包括在将新数据写入数据集时，计算和存储ECC。 该方法包括使用ECC和从ECC导出的第一附加ECC比特来存储是否启用或禁止使用ECC的指示。 该方法包括从数据集读取包括ECC的扩展ECC和从ECC导出的第一附加ECC位，以及根据为数据集存储的指示启用或禁用ECC的使用。 该方法包括使用所述指示和第二附加ECC位使能ECC空白数据集。
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114.发明申请MEMORY DEVICE AND OPERATING METHOD THEREOF FOR REDUCING INTERFERENCE BETWEEN MEMORY CELLS 有权存储器件及其操作方法，用于减少存储器单元之间的干扰公开(公告)号：US20160203878A1
公开(公告)日：2016-07-14
申请号：US14595252
申请日：2015-01-13
Applicant: MACRONIX INTERNATIONAL CO., LTD.
Inventor： Chung-Kuang Chen , Han-Sung Chen , Chun-Hsiung Hung
CPC classification number: G11C29/50016 , G11C7/02 , G11C7/1036 , G11C11/5628 , G11C16/10 , G11C16/12 , G11C16/3427 , G11C16/3459 , G11C19/00 , G11C29/86 , G11C2211/5621
Abstract: An operating method of a memory device comprises the following steps: a first page buffer receives a first input data to be programed into a first memory cell of the memory cells; a second page buffer receives a second input data to be programed into a second memory cell of the memory cells; and the first page buffer determines whether to shift a program verify (PV) voltage for the first input data according to the first and second input data.
Abstract translation: 存储器件的操作方法包括以下步骤：第一页缓冲器接收要被编程到存储器单元的第一存储器单元中的第一输入数据; 第二页缓冲器接收要编程到存储器单元的第二存储单元中的第二输入数据; 并且第一页缓冲器根据第一和第二输入数据确定是否移位用于第一输入数据的程序验证（PV）电压。
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公开(公告)号：US20150370634A1
公开(公告)日：2015-12-24
申请号：US14841950
申请日：2015-09-01
Applicant: MACRONIX INTERNATIONAL CO., LTD.
Inventor： Shih-Chang Huang , Ken-Hui Chen , Chun-Hsiung Hung
CPC classification number: G06F11/1068 , G06F11/1052 , G11C29/52 , G11C2029/0411
Abstract: A method of operating a memory device storing ECCs for corresponding data is provided. The method includes writing an extended ECC during a first program operation, the extended ECC including an ECC and an extended bit derived from the ECC. The method includes overwriting the extended ECC with a pre-determined state during a second program operation to indicate the second program operation. The method includes, setting the ECC to an initial ECC state before the first program operation; during the first program operation, computing the ECC, changing the ECC to the initial ECC state if the computed ECC equals the pre-determined state; and changing the extended bit to an initial value if the ECC equals the initial ECC state. The method includes reading an extended ECC including an extended bit and an ECC for corresponding data, and determining whether to enable ECC logic using the extended ECC.
Abstract translation: 提供一种操作存储用于相应数据的ECC的存储设备的方法。 该方法包括在第一程序操作期间写入扩展ECC，扩展ECC包括ECC和从ECC导出的扩展位。 该方法包括在第二程序操作期间以预定状态重写扩展ECC以指示第二程序操作。 该方法包括：在第一程序操作之前将ECC设置为初始ECC状态; 在第一程序操作期间，如果所计算的ECC等于预定状态，则计算ECC，将ECC改变为初始ECC状态; 并且如果ECC等于初始ECC状态，则将扩展位改变为初始值。 该方法包括读取包括扩展位的扩展ECC和用于相应数据的ECC，并且确定是否使用扩展ECC来启用ECC逻辑。
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Patent Agency Ranking
公开(公告)号：US09214471B2
公开(公告)日：2015-12-15
申请号：US14590273
申请日：2015-01-06
Applicant: MACRONIX INTERNATIONAL CO., LTD.
Inventor： Chun-Hsiung Hung , Shin-Jang Shen , Hang-Ting Lue
IPC: G11C16/04 , G11C16/06 , H01L27/115 , G11C16/10 , H01L27/102 , H01L21/768
CPC classification number: H01L27/11578 , G11C16/0466 , G11C16/0483 , G11C16/10 , H01L21/76838 , H01L27/1021 , H01L27/11582
Abstract: A 3D memory device includes a plurality of ridge-shaped stacks, in the form of multiple strips of conductive material separated by insulating material, arranged as strings which can be coupled through decoding circuits to sense amplifiers. Diodes are connected to the bit line structures at either the string select of common source select ends of the strings. The strips of conductive material have side surfaces on the sides of the ridge-shaped stacks. A plurality of conductive lines arranged as word lines which can be coupled to row decoders, extends orthogonally over the plurality of ridge-shaped stacks. Memory elements lie in a multi-layer array of interface regions at cross-points between side surfaces of the conductive strips on the stacks and the conductive lines.
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公开(公告)号：US09183937B2
公开(公告)日：2015-11-10
申请号：US13936620
申请日：2013-07-08
Applicant: Macronix International Co., Ltd.
Inventor： Ken-Hui Chen , Chun-Hsiung Hung , Kuen-Long Chang
CPC classification number: G11C16/16 , G11C16/345 , G11C16/3454
Abstract: Various aspects of a nonvolatile memory have an improved erase suspend procedure. A bias arrangement is applied to word lines of an erase sector undergoing an erase procedure interrupted by an erase suspend procedure. As a result, another operation performed during erase suspend, such as a read operation or program operation, has more accurate results due to decreased leakage current from any over-erased nonvolatile memory cells of the erase sector.
Abstract translation: 非易失性存储器的各个方面具有改进的擦除暂停过程。 偏移布置被施加到经历由擦除暂停过程中断的擦除过程的擦除扇区的字线。 结果，由于擦除扇区的任何被擦除的非易失性存储单元的漏电流减少，因此在诸如读操作或程序操作的擦除暂停期间执行的另一操作具有更精确的结果。
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118.发明授权公开(公告)号：US09152557B2
公开(公告)日：2015-10-06
申请号：US14265400
申请日：2014-04-30
Applicant: Macronix International Co., Ltd.
Inventor： Lung-Yi Kuo , Hsin-Yi Ho , Chun-Hsiung Hung , Shuo-Nan Hung , Han-Sung Chen
CPC classification number: G06F12/0246 , G06F11/00 , G06F2212/7201 , G06F2212/7203 , G11C16/10 , G11C16/105 , G11C2211/5648
Abstract: A program method for a multi-level cell (MLC) flash memory is provided. The memory array includes a plurality of pages and a plurality of paired pages, which correspond to the respective pages. The program method includes the following steps. Firstly, a program address command is obtained. Next, whether the program address command corresponding to any one of the paired pages is determined. When the program address command corresponds to a first paired page, which corresponds to a first page among the pages, among the paired pages, data stored in the first page to a non-volatile memory are copied. After that, the first paired page is programmed.
Abstract translation: 提供了一种用于多级单元（MLC）闪速存储器的程序方法。 存储器阵列包括对应于各个页面的多个页面和多个配对页面。 程序方法包括以下步骤。 首先，获得程序地址命令。 接下来，确定与配对页中的任何一个对应的程序地址命令。 当程序地址命令对应于对应于页面中的第一页的第一配对页面时，在配对页面中，复制存储在第一页面中的非易失性存储器的数据。 之后，第一个配对的页面被编程。
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公开(公告)号：US09146569B2
公开(公告)日：2015-09-29
申请号：US13862963
申请日：2013-04-15
Applicant: Macronix International Co., Ltd.
Inventor： Chia-Ching Li , Hsien-Hung Wu , Hsin-Yi Ho , Han-Sung Chen , Chun-Hsiung Hung , Tzung-Shen Chen
CPC classification number: G05F1/565
Abstract: A regulator comprises an amplifier, a bias circuit, and a current trimming circuit. The bias circuit is coupled to the amplifier and supplies a first bias current to the amplifier in a first mode of a system including the regulator. The current trimming circuit is coupled to the bias circuit to adjust the first bias current.
Abstract translation: 调节器包括放大器，偏置电路和电流微调电路。 偏置电路耦合到放大器并且在包括调节器的系统的第一模式中向放大器提供第一偏置电流。 电流微调电路耦合到偏置电路以调节第一偏置电流。
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公开(公告)号：US20150220390A1
公开(公告)日：2015-08-06
申请号：US14173873
申请日：2014-02-06
Applicant: Macronix International Co., Ltd.
Inventor： Chien-Hsin Liu , Su-Chueh Lo , Kuen-Long Chang , Ken-Hui Chen , Chun-Hsiung Hung
CPC classification number: G06F11/1072 , G06F11/1012 , H03M13/1575 , H03M13/19
Abstract: A programming method, a reading method and an operating system for a memory are provided. The programming method includes the following steps. A data is provided. A parity generation is performed to obtain an error-correcting code (ECC). The memory is programmed to record the data and the error-correcting code. The data is transformed before performing the parity generation, such that a hamming distance between two codes corresponding to two adjacent threshold voltage states in the data to be performed the parity generation is 1.
Abstract translation: 提供了一种用于存储器的编程方法，读取方法和操作系统。 编程方法包括以下步骤。 提供数据。 执行奇偶校验生成以获得纠错码（ECC）。 存储器被编程为记录数据和纠错码。 在执行奇偶校验生成之前变换数据，使得对应于待执行奇偶产生的数据中的两个相邻阈值电压状态的两个代码之间的汉明距离为1。
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