Patent search ap:("Taiwan Semiconductor Manufacturing Co. Page Ltd.") AND inv:"Tin-Hao Kuo"

111.

发明授权
Integrated circuit packaging substrate, semiconductor package, and manufacturing method 有权

公开(公告)号：US10043774B2

公开(公告)日：2018-08-07

申请号：US14622529

申请日：2015-02-13

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Yu-Wei Lin , Chen-Shien Chen , Guan-Yu Chen , Tin-Hao Kuo , Yen-Liang Lin

IPC: H01L23/00 , H01L23/498 , H01L21/66

Abstract: An integrated circuit (IC) packaging substrate includes a main body, at least one first conductive line, at least one second conductive line, and at least one protrusion pad. The first conductive line is embedded in the main body. The second conductive line is embedded in the main body. The protrusion pad is disposed on the first conductive line. The protrusion pad protrudes from the main body and is configured to be in electrical contact with a solder portion of a semiconductor chip. A first spacing between the protrusion pad and the second conductive line is determined in accordance with a process deviation of the protrusion pad by the width of the protrusion pad and the width of the first conductive line. Moreover, a semiconductor package having the IC packaging substrate and a manufacturing method of the semiconductor package are also provided.

112.

发明授权
Structure and formation method of chip package with fan-out structure 有权

公开(公告)号：US09947552B2

公开(公告)日：2018-04-17

申请号：US15195321

申请日：2016-06-28

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Shing-Chao Chen , Chih-Wei Lin , Meng-Tse Chen , Hui-Min Huang , Ming-Da Cheng , Kuo-Lung Pan , Wei-Sen Chang , Tin-Hao Kuo , Hao-Yi Tsai

IPC: H01L21/56 , H01L21/48 , H01L23/31 , H01L23/58

CPC classification number: H01L21/566 , H01L21/486 , H01L21/561 , H01L21/568 , H01L23/3114 , H01L23/3128 , H01L23/315 , H01L23/585 , H01L24/19 , H01L24/20 , H01L25/105 , H01L25/50 , H01L2224/04105 , H01L2224/12105 , H01L2224/16227 , H01L2224/16235 , H01L2224/32225 , H01L2224/73267 , H01L2224/83005 , H01L2224/92244 , H01L2224/97 , H01L2225/1035 , H01L2225/1041 , H01L2225/1058 , H01L2924/18162 , H01L2224/83 , H01L2224/81

Abstract: Structures and formation methods of a chip package are provided. The method includes forming multiple conductive structures over a carrier substrate and disposing a semiconductor die over the carrier substrate. The method also includes disposing a mold over the carrier substrate. The method further includes forming a protection layer between the mold and the carrier substrate to surround the semiconductor die and the conductive structures. In addition, the method includes removing the mold.

113.

发明申请
BUMP STRUCTURE HAVING A SIDE RECESS AND SEMICONDUCTOR STRUCTURE INCLUDING THE SAME 有权
Title translation: 具有一侧封装的BUMP结构和包括其的半导体结构

公开(公告)号：US20160181223A1

公开(公告)日：2016-06-23

申请号：US15057302

申请日：2016-03-01

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chih-Horng Chang , Tin-Hao Kuo , Chen-Shien Chen , Yen-Liang Lin

IPC: H01L23/00 , H01L25/00

CPC classification number: H01L24/16 , H01L24/11 , H01L24/13 , H01L24/14 , H01L24/81 , H01L25/50 , H01L2224/0401 , H01L2224/05552 , H01L2224/05572 , H01L2224/05599 , H01L2224/10145 , H01L2224/11849 , H01L2224/13011 , H01L2224/13012 , H01L2224/13015 , H01L2224/13018 , H01L2224/13082 , H01L2224/13083 , H01L2224/131 , H01L2224/13147 , H01L2224/14051 , H01L2224/1412 , H01L2224/14152 , H01L2224/14153 , H01L2224/16238 , H01L2224/81191 , H01L2224/81345 , H01L2224/81815 , H01L2924/00014 , H01L2924/01322 , H01L2924/2064 , Y10T428/12493 , Y10T428/24479 , H01L2924/014 , H01L2924/00012 , H01L2924/00

Abstract: In some embodiments, the present invention relates to a method of integrated chip bonding. The method forms a conductive trace on a surface of a first work piece, and a conductive bump on a surface of a second work piece. The conductive bump has a recess. A reflow process is performed on a solder layer to electrically couple the conductive trace and the conductive bump. The solder layer fills a part of the recess during the reflow process. By filling the recess during the reflow process, electrical shorting between the conductive trace and an adjacent conductive is reduced.

Abstract translation: 在一些实施例中，本发明涉及集成芯片接合的方法。该方法在第一工件的表面上形成导电迹线，并在第二工件的表面上形成导电凸块。导电凸块具有凹部。在焊料层上进行回流处理，以电耦合导电迹线和导电凸块。在回流过程中，焊料层填充凹部的一部分。通过在回流工艺期间填充凹槽，导电迹线和相邻导电体之间的电短路减小。

114.

发明申请
INTEGRATED CIRCUIT STRUCTURE AND METHOD 有权

公开(公告)号：US20250096163A1

公开(公告)日：2025-03-20

申请号：US18964949

申请日：2024-12-02

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chen-Hua Yu , Kuo Lung Pan , Tin-Hao Kuo , Hao-Yi Tsai

IPC: H01L23/64 , H01L21/48 , H01L21/56 , H01L21/683 , H01L23/00 , H01L23/31 , H01L23/538

Abstract: A semiconductor device includes a first plurality of dies encapsulated by an encapsulant, an interposer over the first plurality of dies, an interconnect structure over and electrically connected to the interposer, and a plurality of conductive pads on a surface of the interconnect structure opposite the interposer. The interposer includes a plurality of embedded passive components. Each die of the first plurality of dies is electrically connected to the interposer. The interconnect structure includes a solenoid inductor in a metallization layer of the interconnect structure.

115.

发明授权
Bonding passive devices on active dies to form 3D packages 有权

公开(公告)号：US12255174B2

公开(公告)日：2025-03-18

申请号：US17809934

申请日：2022-06-30

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chen-Hua Yu , Kuo Lung Pan , Shu-Rong Chun , Chi-Hui Lai , Tin-Hao Kuo , Hao-Yi Tsai , Chung-Shi Liu

IPC: H01L23/00 , H01L21/56 , H01L23/31 , H01L23/367 , H01L23/498 , H01L23/64 , H01L25/00 , H01L25/065

Abstract: A package includes a package substrate, an interposer over and bonded to the package substrate, a first wafer over and bonding to the interposer, and a second wafer over and bonding to the first wafer. The first wafer has independent passive device dies therein. The second wafer has active device dies therein.

116.

发明授权
Cross-wafer RDLs in constructed wafers 有权

公开(公告)号：US12230513B2

公开(公告)日：2025-02-18

申请号：US18410365

申请日：2024-01-11

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chen-Hua Yu , Tin-Hao Kuo

IPC: H01L21/56 , H01L21/768 , H01L23/00 , H01L23/31 , H01L23/522 , H01L23/538 , H01L25/18

Abstract: A method includes placing a plurality of package components over a carrier, encapsulating the plurality of package components in an encapsulant, forming a light-sensitive dielectric layer over the plurality of package components and the encapsulant, exposing the light-sensitive dielectric layer using a lithography mask, and developing the light-sensitive dielectric layer to form a plurality of openings. Conductive features of the plurality of package components are exposed through the plurality of openings. The method further includes forming redistribution lines extending into the openings. One of the redistribution lines has a length greater than about 26 mm. The redistribution lines, the plurality of package components, the encapsulant in combination form a reconstructed wafer.

117.

发明申请
Integrated Circuit Package and Method 有权

公开(公告)号：US20240371726A1

公开(公告)日：2024-11-07

申请号：US18778763

申请日：2024-07-19

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Shu-Rong Chun , Kuo-Lung Pan , Pei-Hsuan Lee , Chien Ling Hwang , Yu-Chia Lai , Tin-Hao Kuo , Hao-Yi Tsai , Chen-Hua Yu

IPC: H01L23/40 , H01L23/00

Abstract: In an embodiment, a device includes: a package component including integrated circuit dies, an encapsulant around the integrated circuit dies, a redistribution structure over the encapsulant and the integrated circuit dies, and sockets over the redistribution structure; a mechanical brace physically coupled to the sockets, the mechanical brace having openings, each one of the openings exposing a respective one of the sockets; a thermal module physically and thermally coupled to the encapsulant and the integrated circuit dies; and bolts extending through the thermal module, the mechanical brace, and the package component.

118.

发明授权
Three-dimension large system integration 有权

公开(公告)号：US12136612B2

公开(公告)日：2024-11-05

申请号：US17657843

申请日：2022-04-04

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chen-Hua Yu , Tin-Hao Kuo

IPC: H01L25/10 , H01L25/00 , H01L25/18

Abstract: A package includes a building block. The building block includes a device die, an interposer bonded with the device die, and a first encapsulant encapsulating the device die therein. The package further includes a second encapsulant encapsulating the building block therein, and an interconnect structure over the second encapsulant. The interconnect structure has redistribution lines electrically coupling to the device die. A power module is over the interconnect structure. The power module is electrically coupled to the building block through the interconnect structure.