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    Handling ownership of process threads
    111.
    发明授权
    Handling ownership of process threads 有权

    公开(公告)号：US12079657B2

    公开(公告)日：2024-09-03

    申请号：US17356607

    申请日：2021-06-24

    Applicant: Hewlett Packard Enterprise Development LP

    Inventor： Man-Ho Lawrence Lee

    IPC: G06F9/48

    CPC classification number: G06F9/485 ,  G06F9/4881

    Abstract: Examples for handling ownership of process threads include acquiring ownership of a set of process threads to assign ownership of a subject process thread to an ownership agent. In some examples, acquiring ownership may include acquiring ownership of process threads with a wait event. During acquiring ownership of the set of process threads, one or more process threads that are acquired may be released to attend to an event that has occurred. A thread coordinator that handles ownership during acquiring phase may release and rebid one or more process threads. Upon acquiring all the process threads, the ownership of the subject process thread is assigned to an ownership agent. With a set of ownership conditions, the process threads are acquired efficiently within reduced time and with reduced deadlocks.

    Distributed state store supporting multiple protocols
    112.
    发明授权
    Distributed state store supporting multiple protocols 有权

    公开(公告)号：US12079653B2

    公开(公告)日：2024-09-03

    申请号：US17494059

    申请日：2021-10-05

    Applicant: Hewlett Packard Enterprise Development LP

    Inventor： Skyler Thomas ,  Lars Fredriksen ,  Ted Dunning ,  Scott Frolich

    IPC: G06F9/54 ,  G06F9/455 ,  G06F16/182

    CPC classification number: G06F9/45558 ,  G06F9/45516 ,  G06F16/182 ,  G06F2009/45562 ,  G06F2009/4557

    Abstract: Examples described herein are generally directed to facilitating access to container state through multiple protocols. According to an example, a distributed state store is provided in which container state is accessible by multiple client containers via nodes of the distributed state store across which the container state is replicated. Responsive to receipt from a first client container of a storage request via a first application programming interface (API) method of the distributed state store that is associated with a first protocol, the container state is stored within the distributed state store. Responsive to receipt from a second client container of an access request via a second API method of the distributed state store that is associated with a second protocol, the container state is returned to the second client container via the second protocol.

    RATE-LIMITED MECHANISM FOR QUERYING A NON-TABULAR DATABASE
    114.
    发明公开
    RATE-LIMITED MECHANISM FOR QUERYING A NON-TABULAR DATABASE 审中-公开

    公开(公告)号：US20240281554A1

    公开(公告)日：2024-08-22

    申请号：US18172276

    申请日：2023-02-21

    Applicant: Hewlett Packard Enterprise Development LP

    Inventor： Ravi Shekhar Jha ,  Eoghan Shields

    IPC: G06F21/62 ,  G06F16/245

    CPC classification number: G06F21/6227 ,  G06F16/245

    Abstract: Techniques are provided for using rate-limited mechanisms for querying a non-tabular database in a Containers-as-a-Service (CaaS) platform. A vendor-specific request comprising a query path to access a database is received by a keeper service. The query path is validated by the keeper service as being one of a plurality of predefined query paths. Based on the validation, a parameter representing the vendor-specific request is determined by the keeper service to incorporate into a rate-limit calculation, which is performed by the keeper service based on the parameter. Based on the rate limit calculation, a rate limit of the vendor-specific request has not been reached is determined by the keeper service. The vendor-specific request is translated by the keeper service into a vendor-neutral query command based on the type of the database. The vendor-neutral query command is executed, where the vendor-neutral query command provides access to the database.

    Compact screw-latching assembly with overdrive protection
    116.
    发明授权
    Compact screw-latching assembly with overdrive protection 有权

    公开(公告)号：US12066052B2

    公开(公告)日：2024-08-20

    申请号：US17499653

    申请日：2021-10-12

    Applicant: Hewlett Packard Enterprise Development LP

    Inventor： John P. Franz ,  Robert E. Mascia ,  Michael Dustin Scott

    IPC: F16B21/00 ,  F16B5/02 ,  F16B35/04

    CPC classification number: F16B5/0266 ,  F16B35/044

    Abstract: A screw-latching assembly is provided. The assembly includes a screw with a head, a tip, and a body between the head and tip. The body includes a threaded portion adjacent to the tip and an unthreaded portion adjacent to the head, and the unthreaded portion includes a built-in collar with an outer diameter larger than that of the body. The assembly includes a supporting bracket supporting and partially encompassing a first portion of the screw. The supporting bracket includes a base and multiple sidewalls, with a first sidewall comprising a first opening to allow a second portion of the screw to extend out of the supporting bracket and a second sidewall comprising a second opening to allow access to the head by a torquing tool. The assembly includes a spring surrounding at least a portion of the body, with the spring positioned between the built-in collar and the first sidewall.

    Analog error detection and correction in analog in-memory crossbars
    117.
    发明授权
    Analog error detection and correction in analog in-memory crossbars 有权

    公开(公告)号：US12063052B2

    公开(公告)日：2024-08-13

    申请号：US18482964

    申请日：2023-10-09

    Applicant: Hewlett Packard Enterprise Development LP

    Inventor： John Paul Strachan ,  Catherine Graves ,  Can Li

    IPC: H03M13/00 ,  G11C13/00 ,  H03M13/15 ,  G11C27/00 ,  H03M13/11

    CPC classification number: H03M13/6597 ,  G11C13/004 ,  H03M13/1575 ,  G11C13/0069 ,  G11C27/005 ,  H03M13/1177

    Abstract: An analog error correction circuit is disclosed that implements an analog error correction code. The analog circuit includes a crossbar array of memristors or other non-volatile tunable resistive memory devices. The crossbar array includes a first crossbar array portion programmed with values of a target computation matrix and a second crossbar array portion programmed with values of an encoder matrix for correcting computation errors in the matrix multiplication of an input vector with the computation matrix. The first and second crossbar array portions share the same row lines and are connected to a third crossbar array portion that is programmed with values of a decoder matrix, thereby enabling single-cycle error detection. A computation error is detected based on output of the decoder matrix circuitry and a location of the error is determined via an inverse matrix multiplication operation whereby the decoder matrix output is fed back to the decoder matrix.

    Unauthorized data encryption detection
    118.
    发明授权
    Unauthorized data encryption detection 有权

    公开(公告)号：US12061695B2

    公开(公告)日：2024-08-13

    申请号：US17661069

    申请日：2022-04-28

    Applicant: HEWLETT PACKARD ENTERPRISE DEVELOPMENT LP

    Inventor： Joseph E. Algieri ,  Alex Veprinsky

    IPC: G06F21/55 ,  G06F21/56

    CPC classification number: G06F21/554 ,  G06F21/561 ,  G06F2221/034

    Abstract: In some examples, a storage system creates a first copy of a data volume, and receives write requests having a specified characteristic from a host system, the write requests to write data of the data volume, where the storage system is to reject the write requests having the specified characteristic and to accept write requests without the specified characteristic. The storage system maintains metadata for the first copy of the data volume, the metadata indicating blocks of the data volume that have changed since the first copy of the data volume was created. The storage system determines, using the metadata, whether an unauthorized data encryption of the data of the data volume has occurred.

    Computing system having a pivotable front panel
    119.
    发明授权
    Computing system having a pivotable front panel 有权

    公开(公告)号：US12058833B2

    公开(公告)日：2024-08-06

    申请号：US17688548

    申请日：2022-03-07

    Applicant: HEWLETT PACKARD ENTERPRISE DEVELOPMENT LP

    Inventor： Andrew Potter

    IPC: H05K5/02 ,  A47B88/48 ,  A47B88/95 ,  H05K7/14 ,  H05K7/16

    CPC classification number: H05K7/1489 ,  A47B88/48 ,  A47B88/95 ,  H05K7/16

    Abstract: Example implementations relate to a computing system having a chassis and a front panel pivotably coupled to the chassis via a pair of retention brackets. In some examples, the chassis has a pair of frames that is disposed spaced apart and in parallel to each other. Further, each retention bracket of the pair of brackets is movably coupled to a respective frame of the pair of frames. The front panel is releasably engaged to the pair of frames and pivotably coupled to the pair of retention brackets such that the front panel is movable independently relative to the chassis. During installation and maintenance of the computing system, the front panel is movable linearly along a radial direction relative to the pair of frames and rotatable independently relative to the pair of retention brackets so as to provide clearance for accessing interiors of the chassis.

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