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    ELECTRONIC SYSTEM AND METHOD FOR SELECTIVELY ALLOWING ACCESS TO A SHARED MEMORY
    111.
    发明申请
    ELECTRONIC SYSTEM AND METHOD FOR SELECTIVELY ALLOWING ACCESS TO A SHARED MEMORY 有权
    选择性地允许访问共享存储器的电子系统和方法

    公开(公告)号：US20100309211A1

    公开(公告)日：2010-12-09

    申请号：US12857455

    申请日：2010-08-16

    申请人： Jefferson Eugene Owen ,  Raul Zegers Diaz ,  Osvaldo Colavin

    发明人： Jefferson Eugene Owen ,  Raul Zegers Diaz ,  Osvaldo Colavin

    IPC分类号： G06F15/167 ,  H04N7/50

    CPC分类号： G06T1/60 ,  G06F13/1605 ,  G06F13/18 ,  G06F15/167 ,  G09G5/001 ,  G09G5/363 ,  G09G2340/02 ,  G09G2360/18 ,  H04N19/423 ,  H04N19/427 ,  H04N19/61 ,  H04N21/443 ,  H04N21/4435

    摘要： An electronic system, an integrated circuit and a method for display are disclosed. The electronic system contains a first device, a memory and a video/audio compression/decompression device such as a decoder/encoder. The electronic system is configured to allow the first device and the video/audio compression/decompression device to share the memory. The electronic system may be included in a computer in which case the memory is a main memory. Memory access is accomplished by one or more memory interfaces, direct coupling of the memory to a bus, or direct coupling of the first device and decoder/encoder to a bus. An arbiter selectively provides access for the first device and/or the decoder/encoder to the memory based on priority. The arbiter may be monolithically integrated into a memory interface. The decoder may be a video decoder configured to comply with the MPEG-2 standard. The memory may store predicted images obtained from a preceding image.

    摘要翻译： 公开了电子系统，集成电路和显示方法。 电子系统包含第一设备，存储器以及诸如解码器/编码器的视频/音频压缩/解压缩设备。 电子系统被配置为允许第一设备和视频/音频压缩/解压缩设备共享存储器。 电子系统可以包括在计算机中，在这种情况下，存储器是主存储器。 存储器访问由一个或多个存储器接口实现，存储器直接耦合到总线，或者将第一设备和解码器/编码器直接耦合到总线。 仲裁器基于优先级选择性地提供对存储器的第一设备和/或解码器/编码器的访问。 仲裁器可以单片地集成到存储器接口中。 解码器可以是被配置为符合MPEG-2标准的视频解码器。 存储器可以存储从前一图像获得的预测图像。

    Multi-Thread Graphics Processing System
    114.
    发明申请
    Multi-Thread Graphics Processing System 有权
    多线程图形处理系统

    公开(公告)号：US20100156915A1

    公开(公告)日：2010-06-24

    申请号：US12718613

    申请日：2010-03-05

    申请人： Laurent LEFEBVRE ,  Andrew E. GRUBER ,  Stephen L. MOREIN

    发明人： Laurent LEFEBVRE ,  Andrew E. GRUBER ,  Stephen L. MOREIN

    IPC分类号： G06T1/00

    CPC分类号： G06T1/20 ,  G06F9/3851 ,  G06T1/60 ,  G06T15/005 ,  G06T15/04 ,  G09G5/001 ,  G09G5/363

    摘要： A graphics processing system comprises at least one memory device storing a plurality of pixel command threads and a plurality of vertex command threads. An arbiter coupled to the at least one memory device is provided that selects a command thread from either the plurality of pixel or vertex command threads based on relative priorities of the plurality of pixel command threads and the plurality of vertex command threads. The selected command thread is provided to a command processing engine capable of processing pixel command threads and vertex command threads.

    摘要翻译： 图形处理系统包括存储多个像素命令线程和多个顶点命令线程的至少一个存储器件。 提供耦合到所述至少一个存储器件的仲裁器，其基于所述多个像素命令线程和所述多个顶点命令线程的相对优先级从所述多个像素或顶点命令线程中选择命令线程。 所选择的命令线程被提供给能够处理像素命令线程和顶点命令线程的命令处理引擎。

    Display control device and method
    115.
    发明授权
    Display control device and method 有权
    显示控制装置及方法

    公开(公告)号：US07739619B2

    公开(公告)日：2010-06-15

    申请号：US11113030

    申请日：2005-04-25

    申请人： Takuya Sekiguchi ,  Taketo Yoshii ,  Kouichi Yasutake ,  Kazuo Okamura

    发明人： Takuya Sekiguchi ,  Taketo Yoshii ,  Kouichi Yasutake ,  Kazuo Okamura

    IPC分类号： G09G5/00

    CPC分类号： H04N5/44591 ,  G06F3/14 ,  G06F9/5011 ,  G06F2209/506 ,  G09G5/001 ,  G09G5/14 ,  G09G5/39 ,  G09G5/393 ,  G09G2310/04 ,  G09G2340/02 ,  G09G2340/12 ,  G09G2340/125 ,  G09G2360/12 ,  H04N5/4401 ,  H04N5/44543 ,  H04N21/4316 ,  H04N21/4438 ,  H04N21/47214 ,  H04N21/478 ,  H04N21/482 ,  H04N21/4882

    摘要： A display control device for controlling a display of a display device responding to display processing from a plurality of processing units. A display controlling program controls the display device in response to at least one processing unit. The display controlling program receives a request from one processing unit to acquire one of predefined display areas, and determines whether to provide an authorization to acquire one of a plurality of predefined display areas in response to an acquisition request from the one processing unit. When a plurality of requests to acquire the same one of predefined display areas from a plurality of processing units are received, authorization is provided to a single processing unit that made one of the requests to acquire the same one of predefined display areas. The display device is instructed by a processor, based on the display controlling program. A memory, connected to the processor, stores the display controlling program. When an acquisition request for the same one of predefined display areas is received, the processor instructs the display device based on the display controlling program.

    摘要翻译： 一种显示控制装置，用于根据来自多个处理单元的显示处理控制显示装置的显示。 显示控制程序响应于至少一个处理单元控制显示设备。 显示控制程序接收来自一个处理单元的请求以获取预定义的显示区域中的一个，并且响应于来自一个处理单元的获取请求，确定是否提供获取多个预定显示区域中的一个的授权。 当接收到从多个处理单元获取相同的一个预定义显示区域的多个请求时，向单个处理单元提供授权，该单个处理单元使其中一个请求获取预定义的显示区域中相同的一个。 显示装置由处理器基于显示控制程序指示。 连接到处理器的存储器存储显示控制程序。 当接收到对同一个预定义显示区域的获取请求时，处理器基于显示控制程序来指示显示设备。

    Command transfer controlling apparatus and command transfer controlling method
    116.
    发明授权
    Command transfer controlling apparatus and command transfer controlling method 有权
    命令传送控制装置和命令传送控制方法

    公开(公告)号：US07725623B2

    公开(公告)日：2010-05-25

    申请号：US11628684

    申请日：2006-05-10

    申请人： Katsushi Ohtsuka

    发明人： Katsushi Ohtsuka

    IPC分类号： G06F3/00

    CPC分类号： G06F13/1631 ,  G06F13/1642 ,  G06T1/60 ,  G09G5/001 ,  G09G5/395 ,  G09G2360/125 ,  G09G2360/127

    摘要： Commands received from an apparatus that does not support virtual channels are assigned to a virtual channel. A command receiver 210 receives, from an external command transmitting entity that does not support virtual channels, a command designating an address. An assignment information storage unit 228 stores an assignment table in which an address space is divided into a plurality of areas and a channel is assigned to each area. A command storage unit 230 contains queues provided for respective channels, wherein each queue stores received commands temporarily. A distribution destination specifying unit 224 specifies a queue corresponding to an address by referring to the assignment table, and an execution unit 222 transfers the received command to the command storage unit 230 that corresponds to the specified queue.

    摘要翻译： 从不支持虚拟通道的设备接收的命令被分配给虚拟通道。 命令接收器210从不支持虚拟信道的外部命令发送实体接收指定地址的命令。 分配信息存储单元228存储其中地址空间被划分为多个区域并且将频道分配给每个区域的分配表。 命令存储单元230包含针对相应通道提供的队列，其中每个队列临时存储接收到的命令。 分发目的地指定单元224通过参考分配表来指定对应于地址的队列，并且执行单元222将接收的命令传送到与指定队列相对应的命令存储单元230。

    INTEGRATED CIRCUIT FOR CONTROLLING OPERATIONS OF DISPLAY MODULE AND FIRST CIRCUIT MODULE WITH SHARED PIN
    117.
    发明申请
    INTEGRATED CIRCUIT FOR CONTROLLING OPERATIONS OF DISPLAY MODULE AND FIRST CIRCUIT MODULE WITH SHARED PIN 有权
    用于控制显示模块和具有共享PIN的第一个电路模块的操作的集成电路

    公开(公告)号：US20100110066A1

    公开(公告)日：2010-05-06

    申请号：US12408732

    申请日：2009-03-23

    申请人： Yi-Chih Chi ,  Tsai-Tian Huang

    发明人： Yi-Chih Chi ,  Tsai-Tian Huang

    IPC分类号： G09G5/00

    CPC分类号： G09G3/2096 ,  G09G3/3611 ,  G09G5/001 ,  G09G5/393 ,  G09G2360/18

    摘要： An integrated circuit for controlling a display module and a first circuit module with a shared pin includes: a shared pin, a display control module, a first control module, and a pin-sharing management module. The display control module is for controlling operations of the display module, wherein the display module is externally coupled to the integrated circuit via the shared pin. The display control module generates a pin-sharing control signal according to its operating status. The first control module is for controlling operations of the first circuit module, wherein the first circuit module is externally coupled to the integrated circuit via the shared pin. The pin-sharing management module is coupled to the display control module, the first control module and the shared pin and grants one of the display and first control modules access to the shared pin according to the pin-sharing control signal.

    摘要翻译： 用于控制显示模块的集成电路和具有共享引脚的第一电路模块包括：共享引脚，显示控制模块，第一控制模块和引脚共享管理模块。 显示控制模块用于控制显示模块的操作，其中显示模块经由共享引脚外部耦合到集成电路。 显示控制模块根据其工作状态产生引脚共享控制信号。 第一控制模块用于控制第一电路模块的操作，其中第一电路模块经由共享引脚外部耦合到集成电路。 引脚共享管理模块耦合到显示控制模块，第一控制模块和共享引脚，并根据引脚共享控制信号授权显示器和第一控制模块之一访问共享引脚。

    COMMAND PROCESSING APPARATUS, METHOD AND INTEGRATED CIRCUIT APPARATUS
    119.
    发明申请
    COMMAND PROCESSING APPARATUS, METHOD AND INTEGRATED CIRCUIT APPARATUS 有权
    指令处理装置，方法和集成电路装置

    公开(公告)号：US20090327571A1

    公开(公告)日：2009-12-31

    申请号：US12159048

    申请日：2006-07-28

    申请人： Nobuyuki Ichiguchi ,  Tetsuji Mochida ,  Ryuta Nakanishi ,  Takaharu Tanaka

    发明人： Nobuyuki Ichiguchi ,  Tetsuji Mochida ,  Ryuta Nakanishi ,  Takaharu Tanaka

    IPC分类号： G06F12/06

    CPC分类号： G06F3/061 ,  G06F3/0659 ,  G06F3/067 ,  G06F13/1605 ,  G06F13/1647 ,  G06F13/1673 ,  G09G5/001

    摘要： A command processing apparatus and method are provided for optimally processing commands issued asynchronously from a plurality of masters to a storage apparatus including a plurality of banks, where each master issues commands for a bank 0 and a bank 1 alternately. The command processing apparatus includes buffer units that obtain commands issued from the plurality of masters, an arbitration unit that arbitrates the obtained commands, and an issuance unit that issues commands to the storage apparatus according to the arbitration. The arbitration unit reads the commands of the plurality of masters obtained in the buffer units, and selects one command as a result of arbitration. The arbitration unit waits until a next command of a master relating to the selected command becomes readable, and reads the next command. The issuance unit consecutively issues the selected command and the read command to the storage apparatus.

    摘要翻译： 提供了一种命令处理装置和方法，用于最佳地处理从多个主机异步发出的包括多个存储体的存储装置的命令，其中每个主机交替地为存储体0和存储体1发出命令。 命令处理装置包括获取从多个主机发出的命令的缓冲器单元，仲裁所获得的命令的仲裁单元和根据仲裁向存储装置发出命令的发布单元。 仲裁单元读取在缓冲器单元中获得的多个主器件的命令，并且作为仲裁结果选择一个命令。 仲裁单元等待直到与所选择的命令相关的主机的下一个命令变得可读，并读取下一个命令。 发行单元将选择的命令和读取命令连续地发送到存储装置。