公开(公告)号：US08482963B1

公开(公告)日：2013-07-09

申请号：US12629831

申请日：2009-12-02

申请人： Jun Liu ,  Yanzhong Xu ,  Shankar Sinha ,  Shih-Lin S. Lee ,  Jeffrey Xiaoqi Tung ,  Albert Ratnakumar ,  Qi Xiang ,  Irfan Rahim ,  Andy L. Lee ,  Jeffrey T. Watt ,  Srinivas Perisetty

发明人： Jun Liu ,  Yanzhong Xu ,  Shankar Sinha ,  Shih-Lin S. Lee ,  Jeffrey Xiaoqi Tung ,  Albert Ratnakumar ,  Qi Xiang ,  Irfan Rahim ,  Andy L. Lee ,  Jeffrey T. Watt ,  Srinivas Perisetty

IPC分类号： G11C11/00

CPC分类号： G11C11/412

摘要： Asymmetric transistors may be formed by creating pocket implants on one source-drain terminal of a transistor and not the other. Asymmetric transistors may also be formed using dual-gate structures having first and second gate conductors of different work functions. Stacked transistors may be formed by stacking two transistors of the same channel type in series. One of the source-drain terminals of each of the two transistors is connected to a common node. The gates of the two transistors are also connected together. The two transistors may have different threshold voltages. The threshold voltage of the transistor that is located higher in the stacked transistor may be provided with a lower threshold voltage than the other transistor in the stacked transistor. Stacked transistors may be used to reduce leakage currents in circuits such as memory cells. Asymmetric transistors may also be used in memory cells to reduce leakage.

摘要翻译： 不对称晶体管可以通过在晶体管的一个源极 - 漏极端子上而不是另一个产生凹穴注入来形成。 也可以使用具有不同功函数的第一和第二栅极导体的双栅结构来形成非对称晶体管。 可以通过堆叠相同通道类型的两个晶体管串联形成堆叠晶体管。 两个晶体管中的每一个的源极 - 漏极端子之一连接到公共节点。 两个晶体管的栅极也连接在一起。 两个晶体管可以具有不同的阈值电压。 位于堆叠晶体管中较高的晶体管的阈值电压可以具有比堆叠晶体管中的另一个晶体管更低的阈值电压。 堆叠的晶体管可用于减少诸如存储器单元的电路中的漏电流。 不对称晶体管也可用于存储器单元中以减少泄漏。

公开(公告)号：US20130043902A1

公开(公告)日：2013-02-21

申请号：US13214144

申请日：2011-08-19

申请人： Irfan Rahim ,  Jeffrey T. Watt ,  Richard G. Cliff ,  Andy L. Lee ,  Ping-Chen Liu

发明人： Irfan Rahim ,  Jeffrey T. Watt ,  Richard G. Cliff ,  Andy L. Lee ,  Ping-Chen Liu

IPC分类号： H03K19/177

CPC分类号： H03K19/17784 ,  H03K19/17792

摘要： A field programmable gate array (FPGA) includes a set of monitor circuits adapted to provide indications of process, voltage, and temperature for at least one circuit in the FPGA, and a controller adapted to derive a range of body-bias values for the at least one circuit from the indications of process, voltage, and temperature for the at least one circuit. The FPGA further includes a body-bias generator adapted to provide a body-bias signal to at least one transistor in the at least one circuit. The body-bias signal has a value within the range of body-bias values.

摘要翻译： 现场可编程门阵列（FPGA）包括一组监视器电路，其适于为FPGA中的至少一个电路提供过程，电压和温度的指示，以及控制器，其适于导出针对 用于至少一个电路的过程，电压和温度的指示的至少一个电路。 FPGA还包括体偏置发生器，其适于向至少一个电路中的至少一个晶体管提供体偏置信号。 体偏置信号具有在体偏值范围内的值。

公开(公告)号：US20120098569A1

公开(公告)日：2012-04-26

申请号：US13338701

申请日：2011-12-28

申请人： Andy L. Lee ,  Jeffrey T. Watt

发明人： Andy L. Lee ,  Jeffrey T. Watt

IPC分类号： H03K19/173

CPC分类号： H03K19/173 ,  G11C5/005 ,  H01L27/0207 ,  H03K19/1736 ,  H03K19/17784

摘要： Hardened programmable logic devices are provided with programmable circuitry. The programmable circuitry may be hardwired to implement a custom logic circuit. Generic fabrication masks may be used to form the programmable circuitry and may be used in manufacturing a product family of hardened programmable logic devices, each of which may implement a different custom logic circuit. Custom fabrication masks may be used to hardwire the programmable circuitry to implement a specific custom logic circuit. The programmable circuitry may be hardwired in such a way that signal timing characteristics of a hardened programmable logic device that implements a custom logic circuit may match the signal timing characteristics of a programmable logic device that implements the same custom logic circuit using configuration data.

公开(公告)号：US08064280B1

公开(公告)日：2011-11-22

申请号：US12136201

申请日：2008-06-10

申请人： Philip Pan ,  Andy L. Lee ,  Lu Zhou ,  Aniket Kadkol

发明人： Philip Pan ,  Andy L. Lee ,  Lu Zhou ,  Aniket Kadkol

IPC分类号： G11C5/14

CPC分类号： G11C11/418 ,  G11C7/00 ,  G11C7/1045 ,  G11C7/1048 ,  G11C7/12 ,  G11C7/22 ,  G11C8/10 ,  G11C11/4094 ,  G11C11/413 ,  G11C11/419 ,  G11C29/12 ,  G11C2029/0409 ,  G11C2029/1204 ,  G11C2029/2602

摘要： An integrated circuit having a logic element that includes an array of storage elements convertibly functioning as either a configuration random access memory (CRAM) or a static random access memory (SRAM) is provided. The logic element includes first and second pairs of data paths having dedicated multiplexers. In one embodiment, the first and second pairs of data paths are multiplexed into bit lines of a row of the array. The logic element also includes a data path control block generating control signals for each of the dedicated multiplexers. The control signals determine whether the storage elements function as a CRAM or a SRAM. A method for selectively configuring a memory array between a CRAM mode and SRAM mode are provided.

摘要翻译： 提供一种集成电路，其具有包括可转换地用作配置随机存取存储器（CRAM）或静态随机存取存储器（SRAM））的存储元件阵列的逻辑元件。 逻辑元件包括具有专用复用器的第一和第二对数据路径。 在一个实施例中，第一和第二对数据路径被复用到阵列行的位线。 逻辑元件还包括数据路径控制块，其产生用于每个专用多路复用器的控制信号。 控制信号确定存储元件是否用作CRAM或SRAM。 提供了一种用于在CRAM模式和SRAM模式之间选择性地配置存储器阵列的方法。

公开(公告)号：US07839165B2

公开(公告)日：2010-11-23

申请号：US12577061

申请日：2009-10-09

申请人： Michael D. Hutton ,  Andy L. Lee

发明人： Michael D. Hutton ,  Andy L. Lee

IPC分类号： H03K19/173

CPC分类号： H03K19/17748 ,  H03K19/17784

摘要： A programmable logic device (PLD) includes a configuration circuit, and first and second freeze-logic circuits. The configuration circuit provides configuration data for configuring programmable resources of the PLD during a configuration mode of the PLD. One of the two freeze-logic circuits provides a freeze logic signal during the configuration mode of the PLD. The other freeze-logic circuit provides a freeze logic signal during a user mode of the PLD.

摘要翻译： 可编程逻辑器件（PLD）包括配置电路以及第一和第二冻结逻辑电路。 配置电路提供用于在PLD的配置模式期间配置PLD的可编程资源的配置数据。 两个冻结逻辑电路之一在PLD的配置模式期间提供冻结逻辑信号。 另一个冻结逻辑电路在PLD的用户模式期间提供冻结逻辑信号。

公开(公告)号：US07705628B1

公开(公告)日：2010-04-27

申请号：US11486164

申请日：2006-07-12

申请人： Michael D. Hutton ,  Andy L. Lee ,  Gregg William Baeckler ,  Jinyong Yuan ,  Keith Duwel

发明人： Michael D. Hutton ,  Andy L. Lee ,  Gregg William Baeckler ,  Jinyong Yuan ,  Keith Duwel

IPC分类号： G06F7/38 ,  H03K19/173 ,  H03K19/177 ,  H03K19/094 ,  H01L25/00

CPC分类号： H03K19/173 ,  H03K19/1736 ,  H03K19/17728

摘要： A programmable logic device architecture having logic elements with dedicated hardware to configure the look up tables of the logic element to either perform logic functions or to operate as a register for pipelining or other purposes. The programmable logic device includes a general interconnect and a plurality of logic array blocks interconnected by the general interconnect. Each of the plurality of logic blocks further includes one or more logic elements. The logic elements each include a first look up table, a second look up table, and dedicated hardware within the logic element to configure the first look table and the second look up table as a register without having to use the general interconnect. In one embodiment, the dedicated hardware includes a plurality of dedicated interconnects within the logic element to configure the two look up tables as a pair of cross coupled muxes or latches when configured as a register.

摘要翻译： 具有逻辑元件的可编程逻辑器件结构具有专用硬件以配置逻辑元件的查找表以执行逻辑功能或作为流水线或其它目的的寄存器来操作。 可编程逻辑器件包括通用互连和通过一般互连互连的多个逻辑阵列块。 多个逻辑块中的每一个还包括一个或多个逻辑元件。 逻辑元件各自包括第一查询表，第二查询表和逻辑元件内的专用硬件，以将第一查询表和第二查询表配置为寄存器而不必使用通用互连。 在一个实施例中，专用硬件包括逻辑元件内的多个专用互连，以在配置为寄存器时将两个查找表配置为一对交叉耦合的多路复用器或锁存器。

公开(公告)号：US20090282306A1

公开(公告)日：2009-11-12

申请号：US12503637

申请日：2009-07-15

申请人： Ninh D. Ngo ,  Andy L. Lee ,  Kerry Veenstra

发明人： Ninh D. Ngo ,  Andy L. Lee ,  Kerry Veenstra

IPC分类号： G01R31/28

CPC分类号： H03K19/17764 ,  G06F11/1004

摘要： Error detection circuitry is provided on a programmable logic resource. Programmable logic resource configuration data is loaded into a cyclic redundancy check (CRC) module where a checksum calculation may be performed. In one embodiment, the checksum may be compared to an expected value, which is a precomputed checksum on data prior to being programmed into or while data is being programmed into a programmable logic resource. In another embodiment, the expected value may be included in the checksum calculation. An output indicating whether an error is detected may be generated depending on the relationship between the checksum and the expected value, or on the value of the checksum. This output may be sent to an output pin that is accessible by user logic.

摘要翻译： 在可编程逻辑资源上提供错误检测电路。 可编程逻辑资源配置数据被加载到可以执行校验和计算的循环冗余校验（CRC）模块中。 在一个实施例中，校验和可以与预期值进行比较，期望值是在被编程到数据被编程到可编程逻辑资源之前或数据被编程到数据之前的预计算校验和。 在另一个实施例中，期望值可以包括在校验和计算中。 可以根据校验和和期望值之间的关系或校验和的值来生成指示是否检测到错误的输出。 该输出可以被发送到用户逻辑可访问的输出引脚。

公开(公告)号：US07577055B2

公开(公告)日：2009-08-18

申请号：US11930739

申请日：2007-10-31

申请人： Ninh D. Ngo ,  Andy L. Lee ,  Kerry Veenstra

发明人： Ninh D. Ngo ,  Andy L. Lee ,  Kerry Veenstra

IPC分类号： G11C8/00 ,  G01C31/28

CPC分类号： H03K19/17764 ,  G06F11/1004

摘要： Error detection circuitry is provided on a programmable logic resource. Programmable logic resource configuration data is loaded into a cyclic redundancy check (CRC) module where a checksum calculation may be performed. In one embodiment, the checksum may be compared to an expected value, which is a precomputed checksum on data prior to being programmed into or while data is being programmed into a programmable logic resource. In another embodiment, the expected value may be included in the checksum calculation. An output indicating whether an error is detected may be generated depending on the relationship between the checksum and the expected value, or on the value of the checksum. This output may be sent to an output pin that is accessible by user logic.

摘要翻译： 在可编程逻辑资源上提供错误检测电路。 可编程逻辑资源配置数据被加载到可以执行校验和计算的循环冗余校验（CRC）模块中。 在一个实施例中，校验和可以与预期值进行比较，期望值是在被编程到数据被编程到可编程逻辑资源之前或数据被编程到数据之前的预计算校验和。 在另一个实施例中，期望值可以包括在校验和计算中。 可以根据校验和和期望值之间的关系或校验和的值来生成指示是否检测到错误的输出。 该输出可以被发送到用户逻辑可访问的输出引脚。

公开(公告)号：US07571413B1

公开(公告)日：2009-08-04

申请号：US11478148

申请日：2006-06-28

申请人： Jayabrata Ghosh Dastidar ,  Srinivas Perisetty ,  Andy L. Lee

发明人： Jayabrata Ghosh Dastidar ,  Srinivas Perisetty ,  Andy L. Lee

IPC分类号： G06F17/50 ,  H03K19/173

CPC分类号： H03K19/17764 ,  G01R31/318516 ,  G01R31/318575 ,  H03K19/17744 ,  H03K19/17784

摘要： A programmable integrated circuit has multiple power supply voltages. Power supply voltages are distributed using power supply distribution lines. The integrated circuit has programmable power supply voltage selection switches. Each power supply voltage selection switch has its inputs connected to the power supply distribution lines and supplies a selected power supply voltage to a circuit block at its output. Test circuits are provided for testing the power supply voltage selection switches. During testing, the power supply voltage selection switches are adjusted to produce various power supply voltages at their outputs. The test circuit associated with each switch performs voltage comparisons to determine whether the switch is functioning properly. Each test circuit produces a test result based on its voltage comparison. The test results from the test circuits are provided to a scan chain, which unloads the test results from the integrated circuit to a tester for analysis.

摘要翻译： 可编程集成电路具有多个电源电压。 使用电源配电线分配电源电压。 集成电路具有可编程电源电压选择开关。 每个电源电压选择开关的输入连接到电源配线，并将选定的电源电压提供给其输出端的电路块。 提供测试电路用于测试电源电压选择开关。 在测试期间，调整电源电压选择开关，以在其输出端产生各种电源电压。 与每个开关相关的测试电路执行电压比较，以确定开关是否正常工作。 每个测试电路基于其电压比较产生测试结果。 将测试电路的测试结果提供给扫描链，该扫描链将测试结果从集成电路卸载到测试仪进行分析。

公开(公告)号：US20080169836A1

公开(公告)日：2008-07-17

申请号：US11653001

申请日：2007-01-12

申请人： Irfan Rahim ,  Andy L. Lee ,  Myron Wai Wong ,  William Bradley Vest ,  Jeffrey T. Watt

发明人： Irfan Rahim ,  Andy L. Lee ,  Myron Wai Wong ,  William Bradley Vest ,  Jeffrey T. Watt

IPC分类号： H03K19/094 ,  G11C5/02

CPC分类号： H03K19/1776 ,  G11C11/401 ,  G11C11/404 ,  G11C14/00 ,  H03K19/1778

摘要： Integrated circuits such as programmable logic device integrated circuits are provided that have configuration random-access memory elements. The configuration random-access memory elements are loaded with configuration data to customize programmable logic on the integrated circuits. Each memory element has a capacitor that stores data for that memory element. A pair of cross-coupled inverters are connected to the capacitor. The inverters ensure that the memory elements produce output control signals with voltages than range from one power supply rail to another. Each configuration random-access memory element may have a clear transistor. The capacitor may be formed in a dielectric layer that lies above the transistors of the inverters, the address transistor, and the clear transistor. The inverters may be powered with an elevated power supply voltage.

摘要翻译： 提供了诸如可编程逻辑器件集成电路的集成电路，其具有配置随机存取存储器元件。 配置随机存取存储器元件装载有配置数据以在集成电路上定制可编程逻辑。 每个存储器元件具有存储该存储器元件的数据的电容器。 一对交叉耦合的反相器连接到电容器。 逆变器确保存储元件产生的输出控制信号的电压低于从一个电源轨到另一个电源的范围。 每个配置随机存取存储器元件可以具有透明晶体管。 电容器可以形成在位于反相器，地址晶体管和透明晶体管的晶体管之上的电介质层中。 逆变器可以用升高的电源电压供电。