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    INTEGRATED CIRCUIT AND MANUFACTURING METHOD OF COPPER GERMANIDE AND COPPER SILICIDE AS COPPER CAPPING LAYER
    123.
    发明申请
    INTEGRATED CIRCUIT AND MANUFACTURING METHOD OF COPPER GERMANIDE AND COPPER SILICIDE AS COPPER CAPPING LAYER 有权
    铜和铜二氧化硅作为铜箔层的集成电路和制造方法

    公开(公告)号：US20090134521A1

    公开(公告)日：2009-05-28

    申请号：US12264095

    申请日：2008-11-03

    申请人： Chung-Shi Liu ,  Chen-Hua Yu

    发明人： Chung-Shi Liu ,  Chen-Hua Yu

    IPC分类号： H01L23/52 ,  H01L21/44

    CPC分类号： H01L21/76849 ,  H01L21/76846 ,  H01L21/76856 ,  H01L21/76867 ,  H01L21/76886 ,  H01L23/53238 ,  H01L2924/0002 ,  H01L2924/00

    摘要： A method is provided for forming a capping layer comprising Cu, N, and also Si and/or Ge onto a copper conductive structure, said method comprising the sequential steps of: forming, at a temperature range between 200° C. up to 400° C., at least one capping layer onto said copper conductive structure by exposing said structure to a GeH4 and/or a SiH4 comprising ambient, performing a NH3 plasma treatment thereby forming an at least partly nitrided capping layer, forming a dielectric barrier layer onto said at least partly nitrided capping layer, wherein prior to said step of forming said at least one capping layer a pre-annealing step of said copper conductive structure is performed at a temperature range between 250° C. up to 450° C.

    摘要翻译： 提供一种用于在铜导电结构上形成包含Cu，N以及Si和/或Ge的覆盖层的方法，所述方法包括以下顺序步骤：在200℃至400℃的温度范围内 通过将所述结构暴露于包含环境的GeH 4和/或SiH 4，执行NH 3等离子体处理从而形成至少部分氮化的覆盖层，在所述铜导电结构上至少一个覆盖层，在所述铜导电结构上形成介电阻挡层 至少部分氮化的覆盖层，其中在形成所述至少一个覆盖层的所述步骤之前，所述铜导电结构的预退火步骤在250℃至450℃的温度范围内进行。

    Sidewall coverage for copper damascene filling
    124.
    发明授权
    Sidewall coverage for copper damascene filling 有权
    铜镶嵌填料的侧壁覆盖

    公开(公告)号：US07514348B2

    公开(公告)日：2009-04-07

    申请号：US11860639

    申请日：2007-09-25

    申请人： Shau-Lin Shue ,  Mei-Yun Wang ,  Chen-Hua Yu

    发明人： Shau-Lin Shue ,  Mei-Yun Wang ,  Chen-Hua Yu

    IPC分类号： H01L21/302

    CPC分类号： H01L21/76843 ,  H01L21/2855 ,  H01L21/76862 ,  H01L21/76865 ,  H01L21/76873 ,  H01L21/76874 ,  H01L2221/1089

    摘要： A general process is described for filling a hole or trench at the surface of an integrated circuit without trapping voids within the filler material. A particular application is the filling of a trench with copper in order to form damascene wiring. First, a seed layer is deposited in the hole or trench by means of PVD. This is then followed by a sputter etching step which removes any overhang of this seed layer at the mouth of the trench or hole. A number of process variations are described including double etch/deposit steps, varying pressure and voltage in the same chamber to allow sputter etching and deposition to take place without breaking vacuum, and reduction of contact resistance between wiring levels by reducing via depth.

    摘要翻译： 描述了在集成电路的表面处填充孔或沟槽而不在填充材料内捕获空隙的一般方法。 具体应用是用铜填充沟槽以形成镶嵌线。 首先，通过PVD将种子层沉积在孔或沟槽中。 然后进行溅射蚀刻步骤，其移除沟槽或孔口处的该种子层的任何突出端。 描述了许多工艺变化，包括双重蚀刻/沉积步骤，在相同的室中改变压力和电压，以允许在不破坏真空的情况下进行溅射蚀刻和沉积，并且通过减小通孔深度来降低布线水平之间的接触电阻。

    Semiconductor contact structure
    125.
    发明授权
    Semiconductor contact structure 有权
    半导体接触结构

    公开(公告)号：US07466028B1

    公开(公告)日：2008-12-16

    申请号：US11873037

    申请日：2007-10-16

    申请人： Chen-Hua Yu ,  Wen-Chih Chiou ,  Hung-Jung Tu ,  Weng-Jin Wu

    发明人： Chen-Hua Yu ,  Wen-Chih Chiou ,  Hung-Jung Tu ,  Weng-Jin Wu

    IPC分类号： H01L27/10 ,  H01L29/73 ,  H01L29/74 ,  H01L23/02 ,  H01L23/04 ,  H01L23/48 ,  H01L23/52 ,  H01L29/40

    CPC分类号： H01L27/0688 ,  H01L23/481 ,  H01L25/0657 ,  H01L2223/6616 ,  H01L2225/06513 ,  H01L2225/06541 ,  H01L2924/0002 ,  H01L2924/00

    摘要： A semiconductor device structure for a three-dimensional integrated circuit is provided. The semiconductor device structure includes: a substrate having a first surface and a second surface; a via defined in the substrate and extending from the first surface to the second surface; and a first plurality of contact structures on the first surface contacting the via. A cross section of each of the first plurality of contact structures parallel to the first surface has a first side and a second side, and a ratio of the longer side to the shorter side of the first side and the second side is more than about 2:1.

    摘要翻译： 提供了一种用于三维集成电路的半导体器件结构。 半导体器件结构包括：具有第一表面和第二表面的衬底; 通孔，其限定在所述基板中并且从所述第一表面延伸到所述第二表面; 以及在所述第一表面上接触所述通孔的第一多个接触结构。 平行于第一表面的第一多个接触结构中的每一个的横截面具有第一侧和第二侧，并且第一侧和第二侧的长边与短边的比例大于约2 ：1。

    Methods for forming MOS devices with metal-inserted polysilicon gate stack
    126.
    发明申请
    Methods for forming MOS devices with metal-inserted polysilicon gate stack 有权
    用金属插入多晶硅栅极叠层形成MOS器件的方法

    公开(公告)号：US20080299754A1

    公开(公告)日：2008-12-04

    申请号：US11809337

    申请日：2007-05-31

    申请人： Chen-Hua Yu ,  Cheng-Tung Lin ,  Liang-Gi Yao

    发明人： Chen-Hua Yu ,  Cheng-Tung Lin ,  Liang-Gi Yao

    IPC分类号： H01L21/3205

    CPC分类号： H01L29/4966 ,  H01L21/28088 ,  H01L21/823842 ,  H01L29/513 ,  H01L29/517

    摘要： A method for forming a semiconductor structure includes providing a semiconductor substrate; forming a gate dielectric layer on the semiconductor substrate; forming a metal-containing layer on the gate dielectric; and forming a composite layer over the metal-containing layer. The step of forming the composite layer includes forming an un-doped silicon layer substantially free from p-type and n-type impurities; and forming a silicon layer adjoining the un-doped silicon layer. The step of forming the silicon layer comprises in-situ doping a first impurity. (or need to be change to: forming a silicon layer first & then forming un-doped silicon layer) The method further includes performing an annealing to diffuse the first impurity in the silicon layer into the un-doped silicon layer.

    摘要翻译： 一种形成半导体结构的方法包括提供半导体衬底; 在所述半导体衬底上形成栅介电层; 在所述栅极电介质上形成含金属层; 并在该含金属层上形成复合层。 形成复合层的步骤包括形成基本上不含p型和n型杂质的未掺杂硅层; 以及形成邻近所述未掺杂硅层的硅层。 形成硅层的步骤包括原位掺杂第一杂质。 （或者需要改变为：首先形成硅层，然后形成未掺杂的硅层）。该方法还包括执行退火以将硅层中的第一杂质扩散到未掺杂的硅层中。

    Wafer Bonding
    129.
    发明申请
    Wafer Bonding 有权
    晶圆贴合

    公开(公告)号：US20080268614A1

    公开(公告)日：2008-10-30

    申请号：US11740178

    申请日：2007-04-25

    申请人： Ku-Feng Yang ,  Weng-Jin Wu ,  Wen-Chih Chiou ,  Chen-Hua Yu

    发明人： Ku-Feng Yang ,  Weng-Jin Wu ,  Wen-Chih Chiou ,  Chen-Hua Yu

    IPC分类号： H01L21/30

    CPC分类号： H01L21/2007

    摘要： A method for providing a stacked wafer configuration is provided. The method includes bonding a first wafer to a second wafer. A filler material is applied in a gap formed along edges of the first wafer and the second wafer. The filler material provides support along the edges during a thinning and transportation process to help reduce cracking or chipping. The filler material may be cured to reduce any bubbling that may have occurred while applying the filler material. Thereafter, the second wafer may be thinned by grinding, plasma etching, wet etching, or the like. In some embodiments of the present invention, this process may be repeated multiple times to create a stacked wafer configuration having three or more stacked wafers.

    摘要翻译： 提供一种用于提供堆叠晶片配置的方法。 该方法包括将第一晶片接合到第二晶片。 将填料施加在沿着第一晶片和第二晶片的边缘形成的间隙中。 填充材料在减薄和运输过程中沿着边缘提供支撑以帮助减少开裂或碎裂。 可以固化填充材料以减少在施加填充材料时可能发生的任何起泡。 此后，可以通过研磨，等离子体蚀刻，湿蚀刻等来减薄第二晶片。 在本发明的一些实施例中，该过程可以重复多次以产生具有三个或更多个堆叠晶片的堆叠晶片配置。