公开(公告)号：US10593599B2

公开(公告)日：2020-03-17

申请号：US15914547

申请日：2018-03-07

Applicant: GLOBALFOUNDRIES INC.

Inventor： Chanro Park ,  Stan Tsai

IPC: H01L21/8234 ,  H01L21/768 ,  H01L21/311 ,  H01L21/321 ,  H01L27/088 ,  H01L29/45 ,  H01L29/06 ,  H01L21/285 ,  H01L29/08 ,  H01L29/417 ,  H01L29/66

Abstract: The present disclosure relates to semiconductor structures and, more particularly, to contact structures and methods of manufacture. The method includes: recessing an isolation region between adjacent gate structures and below metallization overburden of source/drain metallization; planarizing the metallization overburden to a level of the adjacent gate structures; and forming source/drain contacts to the source/drain metallization, on sides of and extending above the adjacent gate structures.

公开(公告)号：US20200035567A1

公开(公告)日：2020-01-30

申请号：US16047044

申请日：2018-07-27

Applicant: GLOBALFOUNDRIES INC.

Inventor： Daniel Chanemougame ,  Ruilong Xie ,  Chanro Park ,  Guillaume Bouche

IPC: H01L21/8238 ,  H01L27/092

Abstract: A method includes forming an isolation pillar between first and second active nanostructures for adjacent FETs. When a first WFM surrounding the second active nanostructure is removed as part of a WFM patterning process, creating a discontinuity in the first metal. The pillar or the discontinuity in the first metal on the part of the pillar prevent the etching from reaching and removing the first WFM on the first active nanostructure. The isolation pillar creates a gate cut isolation in a selected gate region, and can be shortened in another gate region to allow for gate sharing between adjacent FETs.

公开(公告)号：US20190326165A1

公开(公告)日：2019-10-24

申请号：US15961337

申请日：2018-04-24

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Ruilong Xie ,  Chanro Park ,  Daniel Chanemougame ,  Steven Soss ,  Lars Liebmann ,  Hui Zang ,  Shesh Mani Pandey

IPC: H01L21/768 ,  H01L29/66 ,  H01L29/78 ,  H01L21/8234 ,  H01L23/522 ,  H01L23/528

Abstract: Methods and structures that include a vertical-transport field-effect transistor. First and second semiconductor fins are formed that project vertically from a bottom source/drain region. A first gate stack section is arranged to wrap around a portion of the first semiconductor fin, and a second gate stack section is arranged to wrap around a portion of the second semiconductor fin. The first gate stack section is covered with a placeholder structure. After covering the first gate stack section with the placeholder structure, a metal gate capping layer is deposited on the second gate stack section. After depositing the metal gate capping layer on the second gate stack section, the placeholder structure is replaced with a contact that is connected with the first gate stack section.

公开(公告)号：US10446399B2

公开(公告)日：2019-10-15

申请号：US15339497

申请日：2016-10-31

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Ruilong Xie ,  Min Gyu Sung ,  Chanro Park ,  Hoon Kim

IPC: H01L21/28 ,  H01L29/66 ,  H01L27/088 ,  H01L21/768 ,  H01L21/8234 ,  H01L21/311

Abstract: A method includes providing a starting semiconductor structure, the starting semiconductor structure including a semiconductor substrate with active region(s) separated by isolation regions, the active region(s) including source/drain regions of epitaxial semiconductor material, dummy gate structures adjacent each source/drain region, the dummy gate structures including dummy gate electrodes with spacers adjacent opposite sidewalls thereof and gate caps thereover, and openings between the dummy gate structures. The method further includes filling the openings with a dielectric material, recessing the dielectric material, resulting in a filled and recessed structure, and forming a hard mask liner layer over the filled and recessed structure to protect against loss of the recessed dielectric material during subsequent removal of unwanted dummy gate electrodes. A resulting semiconductor structure formed by the method is also provided.

公开(公告)号：US20190312028A1

公开(公告)日：2019-10-10

申请号：US15948609

申请日：2018-04-09

Applicant: GLOBALFOUNDRIES INC.

Inventor： Chanro Park ,  Ruilong Xie ,  Kangguo Cheng ,  Juntao Li

IPC: H01L27/06 ,  H01L29/78 ,  H01L49/02 ,  H01L21/762 ,  H01L21/8234

Abstract: We report a semiconductor device, containing a semiconductor substrate; an isolation feature on the substrate; a plurality of gates on the isolation feature, wherein each gate comprises a gate electrode and a high-k dielectric layer disposed between the gate electrode and the isolation feature and disposed on and in contact with at least one side of the gate electrode; and a fill metal between the plurality of gates on the isolation feature. We also report methods of forming such a device, and a system for manufacturing such a device.

公开(公告)号：US20190252268A1

公开(公告)日：2019-08-15

申请号：US15897204

申请日：2018-02-15

Applicant: GLOBALFOUNDRIES INC.

Inventor： Ruilong Xie ,  Chanro Park ,  Laertis Economikos ,  Andrew M. Greene ,  Siva Kanakasabapathy ,  John R. Sporre

IPC: H01L21/8238 ,  H01L21/28 ,  H01L29/66 ,  H01L27/092 ,  H01L29/06 ,  H01L29/49

CPC classification number: H01L21/823864 ,  H01L21/28088 ,  H01L21/28185 ,  H01L21/823821 ,  H01L21/823842 ,  H01L21/823878 ,  H01L27/0924 ,  H01L29/0649 ,  H01L29/4966 ,  H01L29/6653 ,  H01L29/66545

Abstract: Gate isolation methods and structures leverage the formation of a sidewall spacer layer within a recess formed in an organic planarization layer. The spacer layer enables precise alignment of the cut region of a sacrificial gate, which may be backfilled with an isolation layer. By forming the isolation layer after a reliability anneal of the gate dielectric and after formation of a first work function metal layer, both the desired critical dimension (CD) and alignment of the isolation layer can be achieved.

公开(公告)号：US10373875B1

公开(公告)日：2019-08-06

申请号：US15928783

申请日：2018-03-22

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Ruilong Xie ,  Daniel Jaeger ,  Chanro Park ,  Laertis Economikos ,  Haiting Wang ,  Hui Zang

IPC: H01L21/8234 ,  H01L29/66 ,  H01L27/088 ,  H01L21/311 ,  H01L21/762

Abstract: Methods of fabricating structures that include contacts coupled with a source/drain region of a field-effect transistor. Source/drain regions are formed adjacent to a temporary gate structure. In one process, a sacrificial layer is disposed over the source/drain regions and a dielectric pillar is formed in the sacrificial layer between the source/drain regions, followed by deposition of a fill material, replacement of the temporary gate structure with a functional gate structure, and removal of the fill material. In another process, the fill material is formed first and the temporary gate structure is replaced by a functional gate structure; following removal of the fill material, a sacrificial layer is disposed over the source/drain regions and a dielectric pillar is formed in the sacrificial layer between the source/drain regions. A conductive layer having separate portions contacting the separate source/drain regions is formed, with the dielectric pillar separating the portions of the conductive layer.

公开(公告)号：US10312154B2

公开(公告)日：2019-06-04

申请号：US15705888

申请日：2017-09-15

Applicant: GLOBALFOUNDRIES INC.

Inventor： Ruilong Xie ,  Steven Bentley ,  Puneet Harischandra Suvarna ,  Chanro Park ,  Min Gyu Sung ,  Lars Liebmann ,  Su Chen Fan ,  Brent Anderson

IPC: H01L21/8238 ,  H01L29/66 ,  H01L29/06 ,  H01L29/78 ,  H01L21/84 ,  H01L21/8234

Abstract: A vertical FinFET includes a semiconductor fin formed over a semiconductor substrate. A self-aligned first source/drain contact is electrically separated from a second source/drain contact by a spacer layer that is formed over an endwall of the fin. The spacer layer, which comprises a dielectric material, allows the self-aligned first source/drain contact to be located in close proximity to an endwall of the fin and the associated second source/drain contact without risk of an electrical short between the adjacent contacts.

公开(公告)号：US10297597B2

公开(公告)日：2019-05-21

申请号：US15689711

申请日：2017-08-29

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Min Gyu Sung ,  Ruilong Xie ,  Chanro Park ,  Murat Kerem Akarvardar

IPC: H01L29/66 ,  H01L27/088 ,  H01L21/8234 ,  H01L21/311 ,  H01L29/06 ,  H01L21/02 ,  H01L21/3105

Abstract: Structures for the isolation of a fin-type field-effect transistor and methods of forming isolation for a fin-type field-effect transistor. A first dielectric layer is formed that encapsulates a plurality of fins. A second dielectric layer is formed that surrounds the first dielectric layer and the plurality of fins. A surface of the second dielectric layer relative to a surface of the first dielectric layer. A liner is conformally deposited on the surface of the first dielectric layer and on the recessed surface of the second dielectric layer. A section of the liner is removed to expose the surface of the first dielectric layer. The exposed surface of the first dielectric layer is recessed to reveal a portion of each of the plurality of fins.

公开(公告)号：US20190148373A1

公开(公告)日：2019-05-16

申请号：US15811961

申请日：2017-11-14

Applicant: GLOBALFOUNDRIES INC.

Inventor： Yongiun Shi ,  Lei Sun ,  Laertis Economikos ,  Ruilong Xie ,  Lars Liebmann ,  Chanro Park ,  Daniel Chanemougame ,  Min Gyu Sung ,  Hsien-Ching Lo ,  Haiting Wang

IPC: H01L27/088 ,  H01L21/8234 ,  H01L21/308 ,  H01L21/762 ,  H01L21/311 ,  H01L29/66 ,  H01L29/06 ,  H01L27/02

CPC classification number: H01L27/0886 ,  H01L21/0276 ,  H01L21/3086 ,  H01L21/31053 ,  H01L21/31116 ,  H01L21/31144 ,  H01L21/76224 ,  H01L21/823431 ,  H01L21/823437 ,  H01L21/823481 ,  H01L27/0207 ,  H01L29/0649 ,  H01L29/66545 ,  H01L29/6656

Abstract: The disclosure provides integrated circuit (IC) structures with single diffusion break (SDB) abutting end isolation regions, and methods of forming the same. An IC structure may include: a plurality of fins positioned on a substrate; a plurality of gate structures each positioned on the plurality of fins and extending transversely across the plurality of fins; an insulator region positioned on the plurality of fins and laterally between the plurality of gate structures; at least one single diffusion break (SDB) positioned within the insulator region and one of the plurality of fins, the at least one SDB region extending from an upper surface of the substrate to an upper surface of the insulator region; and an end isolation region abutting a lateral end of the at least one SDB along a length of the plurality of gate structures, the end isolation region extending substantially in parallel with the plurality of fins.