公开(公告)号：US09822470B2

公开(公告)日：2017-11-21

申请号：US13714990

申请日：2012-12-14

Applicant: INTEL CORPORATION

Inventor： Sasikanth Manipatruni ,  Brian S. Doyle ,  Shawna M. Liff ,  Vivek K. Singh

IPC: D03D1/00 ,  H01B7/04 ,  D02G3/44 ,  D04H3/00 ,  D01D5/00 ,  D01D5/34 ,  B21C37/04 ,  B21C23/08 ,  D04H1/4266 ,  D04H1/4382

CPC classification number: D03D1/0088 ,  B21C23/08 ,  B21C37/042 ,  B21C37/047 ,  D01D5/00 ,  D01D5/34 ,  D02G3/441 ,  D04H1/4266 ,  D04H1/4382 ,  D04H3/00 ,  D10B2401/16 ,  D10B2401/18 ,  Y10T442/3057 ,  Y10T442/603

Abstract: Flexible electronically functional fibers are described that allow for the placement of electronic functionality in traditional fabrics. The fibers can be interwoven with natural fibers to produce electrically functional fabrics and devices that can retain their original appearance.

公开(公告)号：US20170256707A1

公开(公告)日：2017-09-07

申请号：US15519810

申请日：2014-12-18

Applicant: INTEL CORPORATION

Inventor： David Michalak ,  Sasikanth Manipatruni ,  James Clarke ,  Dmitri Nikonov ,  Ian Young

IPC: H01L43/10 ,  G01D5/20 ,  H01L43/12 ,  H01L43/02 ,  H01L43/08

CPC classification number: H01L43/10 ,  G01D5/2033 ,  G01R33/1284 ,  G11B5/3993 ,  G11B2005/3996 ,  H01L43/02 ,  H01L43/08 ,  H01L43/12

Abstract: Described is a method comprising: forming a magnet on a substrate or a template, the magnet having an interface; and forming a first layer of non-magnet conductive material on the interface of the magnet such that the magnet and the layer of non-magnet conductive material are formed in-situ. Described is an apparatus comprising: a magnet formed on a substrate or a template, the magnet being formed under crystallographic, electromagnetic, or thermodynamic conditions, the magnet having an interface; and a first layer of non-magnet conductive material formed on the interface of the magnet such that the magnet and the layer of non-magnet conductive material are formed in-situ.

公开(公告)号：US09391262B1

公开(公告)日：2016-07-12

申请号：US14139528

申请日：2013-12-23

Applicant: Intel Corporation

Inventor： Dmitri E. Nikonov ,  Sasikanth Manipatruni ,  Ian A Young

IPC: H01L29/82 ,  H01L43/04

CPC classification number: H01L43/04 ,  G11C11/161 ,  G11C11/1673 ,  G11C11/1675 ,  G11C11/18 ,  H01L27/228 ,  H01L43/08 ,  H01L43/10

Abstract: Described are Spin Hall Magnetic Random Access Memory (MRAM) cells and arrays. In one embodiment, an apparatus includes a nanomagnet having a cross-sectional area and a spin Hall effect (SHE) material. The SHE material is coupled to a subset of the cross-sectional area of the nanomagnet.

Abstract translation: 描述了旋转霍尔磁随机存取存储器（MRAM）单元和阵列。 在一个实施例中，装置包括具有横截面积和旋转霍尔效应（SHE）材料的纳米磁体。 SHE材料耦合到纳米磁体的横截面积的子集。

公开(公告)号：US12001941B2

公开(公告)日：2024-06-04

申请号：US16194792

申请日：2018-11-19

Applicant: Intel Corporation

Inventor： Dmitri E. Nikonov ,  Sasikanth Manipatruni ,  Ian A. Young

IPC: G06N3/049 ,  G06N3/045 ,  G06N3/08

CPC classification number: G06N3/049 ,  G06N3/045 ,  G06N3/08

Abstract: Embodiments may relate to a system to be used in an oscillating neural network (ONN). The system may include a control node and a plurality of nodes wirelessly communicatively coupled with a control node. A node of the plurality of nodes may be configured to identify an oscillation frequency of the node based on a weight W and an input X. The node may further be configured to transmit a wireless signal to the control node, wherein a frequency of the wireless signal oscillates based on the identified oscillation frequency. Other embodiments may be described or claimed.

公开(公告)号：US11818963B2

公开(公告)日：2023-11-14

申请号：US17578093

申请日：2022-01-18

Applicant: Intel Corporation

Inventor： Sasikanth Manipatruni ,  Kaan Oguz ,  Chia-Ching Lin ,  Christopher Wiegand ,  Tanay Gosavi ,  Ian Young

IPC: H10N50/80 ,  H01F10/32 ,  G11C11/16 ,  H10B61/00 ,  H10N50/85

CPC classification number: H10N50/80 ,  G11C11/161 ,  H01F10/329 ,  H01F10/3268 ,  H01F10/3286 ,  H10B61/22 ,  H10N50/85

Abstract: An apparatus is provided which comprises: a magnetic junction including: a stack of structures including: a first structure comprising a magnet with an unfixed perpendicular magnetic anisotropy (PMA) relative to an x-y plane of a device, wherein the first structure has a first dimension along the x-y plane and a second dimension in the z-plane, wherein the second dimension is substantially greater than the first dimension. The magnetic junction includes a second structure comprising one of a dielectric or metal; and a third structure comprising a magnet with fixed PMA, wherein the third structure has an anisotropy axis perpendicular to the plane of the device, and wherein the third structure is adjacent to the second structure such that the second structure is between the first and third structures; and an interconnect adjacent to the third structure, wherein the interconnect comprises a spin orbit material.

公开(公告)号：US11683939B2

公开(公告)日：2023-06-20

申请号：US16396451

申请日：2019-04-26

Applicant: Intel Corporation

Inventor： Benjamin Buford ,  Angeline Smith ,  Noriyuki Sato ,  Tanay Gosavi ,  Kaan Oguz ,  Christopher Wiegand ,  Kevin O'Brien ,  Tofizur Rahman ,  Gary Allen ,  Sasikanth Manipatruni ,  Emily Walker

IPC: H10B61/00 ,  H10N50/10 ,  H10N52/00 ,  H10N52/01 ,  H10N52/80

CPC classification number: H10B61/22 ,  H10N50/10 ,  H10N52/00 ,  H10N52/01 ,  H10N52/80

Abstract: A memory apparatus includes a first electrode having a spin orbit material. The memory apparatus further includes a first memory device on a portion of the first electrode and a first dielectric adjacent to a sidewall of the first memory device. The memory apparatus further includes a second memory device on a portion of the first electrode and a second dielectric adjacent to a sidewall of the second memory device. A second electrode is on and in contact with a portion of the first electrode, where the second electrode is between the first memory device and the second memory device. The second electrode has a lower electrical resistance than an electrical resistance of the first electrode. The memory apparatus further includes a first interconnect structure and a second interconnect, each coupled with the first electrode.

公开(公告)号：US11444237B2

公开(公告)日：2022-09-13

申请号：US16024393

申请日：2018-06-29

Applicant: Intel Corporation

Inventor： Noriyuki Sato ,  Tanay Gosavi ,  Gary Allen ,  Sasikanth Manipatruni ,  Kaan Oguz ,  Kevin O'Brien ,  Christopher Wiegand ,  Angeline Smith ,  Tofizur Rahman ,  Ian Young ,  Ben Buford

IPC: H01L43/02 ,  H01L43/12 ,  H01L27/22 ,  G11C11/16 ,  H01F10/32 ,  H01L43/10 ,  G11C11/14

Abstract: A spin orbit torque (SOT) memory device includes a SOT electrode having a spin orbit coupling material. The SOT electrode has a first sidewall and a second sidewall opposite to the first sidewall. The SOT memory device further includes a magnetic tunnel junction device on a portion of the SOT electrode. A first MTJ sidewall intersects the first SOT sidewall and a portion of the first MTJ sidewall and the SOT sidewall has a continuous first slope. The MTJ device has a second sidewall that does not extend beyond the second SOT sidewall and at least a portion of the second MTJ sidewall has a second slope.

公开(公告)号：US11417830B2

公开(公告)日：2022-08-16

申请号：US16024709

申请日：2018-06-29

Applicant: Intel Corporation

Inventor： Tanay Gosavi ,  Sasikanth Manipatruni ,  Chia-Ching Lin ,  Gary Allen ,  Kaan Oguz ,  Kevin O'Brien ,  Noriyuki Sato ,  Ian Young ,  Dmitri Nikonov

IPC: H01L43/02 ,  H01L27/22 ,  G11C11/16 ,  H01L43/12 ,  H01L43/10

Abstract: Embodiments herein relate to magnetically doping a spin orbit torque electrode (SOT) in a magnetic random access memory apparatus. In particular, the apparatus may include a free layer of a magnetic tunnel junction (MTJ) coupled to a SOT electrode that is magnetically doped to apply an effective magnetic field on the free layer, where the free layer has a magnetic polarization in a first direction and where current flowing through the magnetically doped SOT electrode is to cause the magnetic polarization of the free layer to change to a second direction that is substantially opposite to the first direction.

公开(公告)号：US11387404B2

公开(公告)日：2022-07-12

申请号：US16130905

申请日：2018-09-13

Applicant: Intel Corporation

Inventor： Huichu Liu ,  Tanay Karnik ,  Sasikanth Manipatruni ,  Daniel Morris ,  Kaushik Vaidyanathan ,  Ian Young

IPC: G11C11/00 ,  H01L43/02 ,  H01L43/10 ,  H01L43/06 ,  G11C11/16 ,  G11C11/18

Abstract: An apparatus is provided which comprises one or more magnetoelectric spin orbit (MESO) minority gates with different peripheral complementary metal oxide semiconductor (CMOS) circuit techniques in the device layer including: (1) current mirroring, (2) complementary supply voltages, (3) asymmetrical transistor sizing, and (4) using transmission gates. These MESO minority gates use the multi-phase clock to prevent back propagation of current so that MESO gate can correctly process the input data.

公开(公告)号：US11374164B2

公开(公告)日：2022-06-28

申请号：US16024714

申请日：2018-06-29

Applicant: Intel Corporation

Inventor： Tanay Gosavi ,  Sasikanth Manipatruni ,  Chia-Ching Lin ,  Kaan Oguz ,  Christopher Wiegand ,  Angeline Smith ,  Noriyuki Sato ,  Kevin O'Brien ,  Benjamin Buford ,  Ian Young ,  Md Tofizur Rahman

IPC: H01L43/02 ,  H01L27/22 ,  H01L43/12

Abstract: Embodiments herein relate to a system, apparatus, and/or process for producing a spin orbit torque (SOT) electrode that includes a first layer with a first side to couple with a free layer of a magnetic tunnel junction (MTJ) and a second layer coupled with a second side of the first layer opposite the first side, where a value of an electrical resistance in the first SOT layer is lower than a value of an electrical resistance in the second SOT layer and where a current applied to the SOT electrode is to cause current to preferentially flow in the first SOT layer to cause a magnetic polarization of the free layer to change directions. During production of the SOT electrode, the second layer may act as an etch stop.