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    ECC METHOD FOR FLASH MEMORY
    121.
    发明申请
    ECC METHOD FOR FLASH MEMORY 有权
    闪存存储器的ECC方法

    公开(公告)号：US20150205665A1

    公开(公告)日：2015-07-23

    申请号：US14158613

    申请日：2014-01-17

    Applicant: Macronix International Co., Ltd.

    Inventor： Nai-Ping Kuo ,  Shih-Chang Huang ,  Chin-Hung Chang ,  Ken-Hui Chen ,  Kuen-Long Chang ,  Chun-Hsiung Hung

    IPC: G06F11/10

    CPC classification number: G06F11/1048 ,  G06F2212/1036 ,  G11C16/3436

    Abstract: A method of operating a memory storing data sets, and ECCs for the data sets is provided. The method includes when writing new data in a data set, computing and storing an ECC, if a number of addressable segments storing the new data and data previously programmed in the data set includes at least a predetermined number of addressable segments. The method includes storing indications for whether to enable or disable use of the ECCs, using the ECC and a first additional ECC bit derived from the ECC. The method includes reading from a data set an extended ECC including an ECC and a first additional ECC bit derived from the ECC, and enabling or disabling use of the ECC according to the indications stored for the data set. The method includes enabling use of ECCs for blank data sets, using the indications and a second additional ECC bit.

    Abstract translation: 提供了一种操作存储数据集的存储器和数据集的ECC的方法。 如果存储新数据的多个可寻址段和先前在数据集中编程的数据包括至少预定数量的可寻址段，则该方法包括在将新数据写入数据集时，计算和存储ECC。 该方法包括使用ECC和从ECC导出的第一附加ECC比特来存储是否启用或禁止使用ECC的指示。 该方法包括从数据集读取包括ECC的扩展ECC和从ECC导出的第一附加ECC位，以及根据为数据集存储的指示启用或禁用ECC的使用。 该方法包括使用所述指示和第二附加ECC位使能ECC空白数据集。

    METHOD AND APPARATUS FOR ADJUSTING DRAIN BIAS OF A MEMORY CELL WITH ADDRESSED AND NEIGHBOR BITS
    122.
    发明申请
    METHOD AND APPARATUS FOR ADJUSTING DRAIN BIAS OF A MEMORY CELL WITH ADDRESSED AND NEIGHBOR BITS 审中-公开
    用于调整具有寻址和邻居位置的存储单元的漏磁偏移的方法和装置

    公开(公告)号：US20150085588A1

    公开(公告)日：2015-03-26

    申请号：US14556973

    申请日：2014-12-01

    Applicant: Macronix International Co., Ltd.

    Inventor： Han-Sung Chen ,  Chung-Kuang Chen ,  Chun-Hsiung Hung

    IPC: G11C7/00

    CPC classification number: G11C7/00 ,  G11C11/5628 ,  G11C11/5642 ,  G11C11/5671 ,  G11C2211/5621

    Abstract: The storage layer such as a nitride layer of a nonvolatile memory cell has two storage parts storing separately addressable data, typically respectively proximate to the source terminal and the drain terminal. The applied drain voltage while sensing the data of one of the storage parts depends on the data stored at the other storage part. If the data stored at the other storage part is represented by a threshold voltage exceeding a minimum threshold voltage, then the applied drain voltage is raised. This technology is useful in read operations and program verify operations to widen the threshold voltage window.

    Abstract translation: 诸如非易失性存储单元的氮化物层的存储层具有存储单独可寻址数据的两个存储部分，通常分别靠近源极端子和漏极端子。 在感测一个存储部件的数据时所施加的漏极电压取决于存储在另一个存储部分的数据。 如果存储在另一个存储部分的数据由超过最小阈值电压的阈值电压表示，则所施加的漏极电压升高。 该技术在读取操作和程序验证操作中有助于拓宽阈值电压窗口。

    Word line driver circuit for selecting and deselecting word lines
    123.
    发明授权
    Word line driver circuit for selecting and deselecting word lines 有权
    用于选择和取消选择字线的字线驱动电路

    公开(公告)号：US08976600B2

    公开(公告)日：2015-03-10

    申请号：US14046428

    申请日：2013-10-04

    Applicant: Macronix International Co., Ltd.

    Inventor： Chun-Hsiung Hung ,  Ti Wen Chen ,  Shuo-Nan Hung ,  Shih-Lin Huang

    IPC: G11C16/06 ,  G11C16/16

    CPC classification number: G11C16/16 ,  G11C16/08 ,  G11C16/12

    Abstract: A memory circuit includes word lines coupled to a memory array, including a first set of one or more word lines deselected in an erase operation, and a second set of one or more word lines selected in the erase operation. Control circuitry couples the first set of one or more word lines deselected in the erase operation to a reference voltage, responsive to receiving an erase command for the erase operation. Some examples further include a first transistor that switchably couples a word line to a global word line, and a second transistor that switchably couples the word line to a ground voltage. The control circuitry is coupled to the first transistor and the second transistor, wherein the control circuitry has a plurality of modes including at least an erase operation. In a first mode, the first transistor couples the word line to the global word line, and the second transistor decouples the word line from the ground voltage. In a second mode, the first transistor decouples the word line from the global word line, and the second transistor couples the word line to the ground voltage.

    Abstract translation: 存储电路包括耦合到存储器阵列的字线，包括在擦除操作中取消选择的一个或多个字线的第一组以及在擦除操作中选择的一个或多个字线的第二组。 响应于接收到擦除操作的擦除命令，控制电路将擦除操作中未选择的一个或多个字线的第一组耦合到参考电压。 一些示例还包括可将字线可切换地耦合到全局字线的第一晶体管，以及可切换地将字线耦合到接地电压的第二晶体管。 控制电路耦合到第一晶体管和第二晶体管，其中控制电路具有包括至少擦除操作的多个模式。 在第一模式中，第一晶体管将字线耦合到全局字线，并且第二晶体管将字线与接地电压分离。 在第二模式中，第一晶体管将字线与全局字线分离，并且第二晶体管将字线耦合到接地电压。

    METHOD AND APPARATUS FOR REDUCING ERASE TIME OF MEMORY BY USING PARTIAL PRE-PROGRAMMING
    124.
    发明申请
    METHOD AND APPARATUS FOR REDUCING ERASE TIME OF MEMORY BY USING PARTIAL PRE-PROGRAMMING 审中-公开
    通过使用部分预编程减少存储器擦除时间的方法和装置

    公开(公告)号：US20150036436A1

    公开(公告)日：2015-02-05

    申请号：US14518645

    申请日：2014-10-20

    Applicant: Macronix International Co., Ltd.

    Inventor： Chun-Yi Lee ,  Kuen-Long Chang ,  Chun-Hsiung Hung

    IPC: G11C16/14

    CPC classification number: G11C16/14 ,  G11C16/16 ,  G11C16/344

    Abstract: Memory cells of a nonvolatile memory array are characterized by one of multiple threshold voltage ranges including at least an erased threshold voltage range and a programmed threshold voltage range. Responsive to an erase command to erase a group of memory cells of the nonvolatile memory array, a plurality of phases are performed, including at least a pre-program phase and an erase phase. The pre-program phase programs a first set of memory cells in the group having threshold voltages within the erased threshold voltage range, and does not program a second set of memory cells in the group having threshold voltages within the erased threshold voltage range in the group. By not programming the second set of memory cells, the pre-program phase is performed more quickly than if the second set of memory cells were programmed along with the first set of memory cells.

    Abstract translation: 非易失性存储器阵列的存储单元的特征在于包括至少一个擦除的阈值电压范围和编程的阈值电压范围的多个阈值电压范围之一。 响应于擦除非易失性存储器阵列的一组存储单元的擦除命令，执行至少包括预编程相位和擦除阶段的多个相位。 预编程相位对组内的阈值电压中的第一组存储器单元进行编程，并且不对组中擦除的阈值电压范围内的阈值电压的组中的第二组存储器单元进行编程 。 通过不对第二组存储器单元进行编程，如果第二组存储器单元与第一组存储器单元一起被编程，那么执行预编程相位更快。

    Memory architecture of 3D array with diode in memory string
    125.
    发明授权
    Memory architecture of 3D array with diode in memory string 有权
    具有二极管在内存字符串的3D阵列的内存架构

    公开(公告)号：US08947936B2

    公开(公告)日：2015-02-03

    申请号：US14166471

    申请日：2014-01-28

    Applicant: Macronix International Co., Ltd.

    Inventor： Chun-Hsiung Hung ,  Shin-Jang Shen ,  Hang-Ting Lue

    IPC: G11C16/04 ,  G11C16/06 ,  H01L27/115 ,  G11C16/10 ,  H01L27/102

    CPC classification number: H01L27/11578 ,  G11C16/0466 ,  G11C16/0483 ,  G11C16/10 ,  H01L21/76838 ,  H01L27/1021 ,  H01L27/11582

    Abstract: A 3D memory device includes a plurality of ridge-shaped stacks, in the form of multiple strips of conductive material separated by insulating material, arranged as strings which can be coupled through decoding circuits to sense amplifiers. Diodes are connected to the bit line structures at either the string select of common source select ends of the strings. The strips of conductive material have side surfaces on the sides of the ridge-shaped stacks. A plurality of conductive lines arranged as word lines which can be coupled to row decoders, extends orthogonally over the plurality of ridge-shaped stacks. Memory elements lie in a multi-layer array of interface regions at cross-points between side surfaces of the conductive strips on the stacks and the conductive lines.

    Abstract translation: 3D存储器件包括多个由绝缘材料隔开的多条导电材料形式的脊状叠层，布置成可以通过解码电路耦合到读出放大器的串。 在字符串的公共源选择端的字符串选择处，二极管连接到位线结构。 导电材料条具有在脊形叠层的侧面上的侧表面。 布置成可以连接到行解码器的字线的多条导线垂直地延伸在多个脊形叠层上。 存储器元件位于叠层和导电线上的导电条的侧表面之间的交叉点处的界面区域的多层阵列。

    METHOD AND APPARATUS FOR MEMORY REPAIR
    127.
    发明申请
    METHOD AND APPARATUS FOR MEMORY REPAIR 有权
    用于记忆修复的方法和装置

    公开(公告)号：US20140254297A1

    公开(公告)日：2014-09-11

    申请号：US14036997

    申请日：2013-09-25

    Applicant: Macronix International Co., Ltd.

    Inventor： Shuo-Nan Hung ,  Chi Lo ,  Chun-Hsiung Hung

    IPC: G11C29/04

    CPC classification number: G11C29/70 ,  G11C29/04 ,  G11C29/72 ,  G11C29/808 ,  G11C29/82

    Abstract: An integrated circuit includes an array of memory cells that is arranged into rows, main columns, and redundant columns that perform repairs in the array. The main columns and the redundant columns are divided into row blocks. Bit lines couple the main columns to status memory indicating repair statuses of the repairs by the redundant columns. The integrated circuit receives a command, and performs an update on the status memory with the repair statuses specific to particular ones of the row blocks in a portion of the memory accessed by the command. Alternatively or in combination, the status memory has insufficient size to store the repair statuses of multiple ones of the row blocks of the main columns.

    Abstract translation: 集成电路包括排列成在阵列中执行维修的行，主列和冗余列的存储器单元阵列。 主列和冗余列分为行块。 位线将主列连接到指示冗余列修复状态的状态存储器。 集成电路接收命令，并且利用该命令访问的存储器的一部分中的特定行的特定块的修复状态对状态存储器进行更新。 或者或组合地，状态存储器的尺寸不足以存储主列的多个行块的修复状态。

    MEMORY PAGE BUFFER
    130.
    发明申请
    MEMORY PAGE BUFFER 审中-公开
    内存页缓冲区

    公开(公告)号：US20130235674A1

    公开(公告)日：2013-09-12

    申请号：US13871891

    申请日：2013-04-26

    Applicant: MACRONIX INTERNATIONAL CO., LTD.

    Inventor： Chun-Hsiung Hung ,  Chi Lo

    IPC: G11C16/28 ,  G11C16/26

    CPC classification number: G11C16/26 ,  G11C11/56 ,  G11C16/0483 ,  G11C16/06 ,  G11C16/10 ,  G11C16/28 ,  Y10T29/49117

    Abstract: Various embodiments address various difficulties with source side sensing difficulties in various memory architectures, such as 3D vertical gate flash and multilevel cell memory. One such difficulty is that with source side sensing, the signal amplitude is significantly smaller than drain side sensing. Another such difficulty is the noise and reduced sensing margins associated with multilevel cell memory. In some embodiments the bit line is selectively discharged prior to applying the read bias arrangement.

    Abstract translation: 各种实施例解决了诸如3D垂直门闪存和多电平单元存储器的各种存储器架构中的源侧感测困难的各种困难。 一个这样的困难是，通过源侧感测，信号幅度显着小于漏极侧感测。 另一个这样的困难是与多电平单元存储器相关联的噪声和降低的感测裕度。 在一些实施例中，位线在施加读取偏置布置之前被选择性地放电。

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