公开(公告)号：US09461155B2

公开(公告)日：2016-10-04

申请号：US14028242

申请日：2013-09-16

Applicant: Micron Technology, Inc.

Inventor： Sanh D. Tang ,  John K. Zahurak ,  Michael P. Violette

IPC: H01L21/332 ,  H01L29/74 ,  H01L27/102 ,  H01L29/423 ,  H01L29/66

CPC classification number: H01L29/66363 ,  H01L27/1027 ,  H01L29/42308 ,  H01L29/74 ,  H01L2924/1301

Abstract: Memory devices and methods of making memory devices are shown. Methods and configurations as shown provide folded and vertical memory devices for increased memory density. Methods provided reduce a need for manufacturing methods such as deep dopant implants.

公开(公告)号：US09379005B2

公开(公告)日：2016-06-28

申请号：US14041928

申请日：2013-09-30

Applicant: Micron Technology, Inc.

Inventor： Sanh D. Tang ,  John K. Zahurak

IPC: H01L21/331 ,  H01L21/336 ,  H01L21/82 ,  H01L21/768 ,  H01L27/06 ,  H01L27/115 ,  H01L27/24 ,  H01L29/66 ,  H01L29/788 ,  H01L29/792 ,  H01L21/28 ,  H01L45/00

CPC classification number: H01L27/11582 ,  G11C13/004 ,  G11C13/0069 ,  G11C13/0097 ,  G11C16/10 ,  G11C16/14 ,  G11C16/26 ,  G11C2213/71 ,  H01L21/28273 ,  H01L21/76838 ,  H01L23/528 ,  H01L27/0688 ,  H01L27/11519 ,  H01L27/11548 ,  H01L27/11551 ,  H01L27/11556 ,  H01L27/11565 ,  H01L27/11575 ,  H01L27/11578 ,  H01L27/2454 ,  H01L27/249 ,  H01L29/66825 ,  H01L29/66833 ,  H01L29/7889 ,  H01L29/7926 ,  H01L45/06

Abstract: Some embodiments include a memory device and methods of forming the memory device. One such memory device includes a first group of memory cells, each of the memory cells of the first group being formed in a cavity of a first control gate located in one device level of the memory device. The memory device also includes a second group of memory cells, each of the memory cells of the second group being formed in a cavity of a second control gate located in another device level of the memory device. Additional apparatus and methods are described.

Abstract translation: 一些实施例包括存储器件和形成存储器件的方法。 一个这样的存储器件包括第一组存储器单元，第一组的每个存储器单元形成在位于存储器件的一个器件级中的第一控制栅极的空腔中。 存储器件还包括第二组存储器单元，第二组的每个存储器单元形成在位于存储器件的另一个器件级中的第二控制栅极的腔中。 描述附加的装置和方法。

公开(公告)号：US20160155745A1

公开(公告)日：2016-06-02

申请号：US15005360

申请日：2016-01-25

Applicant: Micron Technology, Inc.

Inventor： Sanh D. Tang ,  Kamal M. Karda ,  Wolfgang Mueller ,  Sourabh Dhir ,  Robert Kerr ,  Sangmin Hwang ,  Haitao Liu

IPC: H01L27/108 ,  H01L29/06 ,  H01L23/528

CPC classification number: H01L27/10823 ,  H01L21/76232 ,  H01L23/528 ,  H01L27/10808 ,  H01L27/10876 ,  H01L27/10885 ,  H01L27/10888 ,  H01L29/0649 ,  H01L29/0653 ,  H01L29/66477 ,  H01L29/66621 ,  H01L29/78 ,  H01L2924/0002 ,  H01L2924/1436 ,  H01L2924/00

Abstract: An array of recessed access gate lines includes active area regions having dielectric trench isolation material there-between. The trench isolation material comprises dielectric projections extending into opposing ends of individual active area regions under an elevationally outermost surface of material of the active area regions. The active area material is elevationally over the dielectric projections. Recessed access gate lines individually extend transversally across the active area regions and extend between the ends of immediately end-to-end adjacent active area regions within the dielectric trench isolation material. Other arrays are disclosed, as are methods.

Abstract translation: 一组凹进的存取栅极线包括其间具有介电沟槽隔离材料的有源区域区域。 沟槽隔离材料包括延伸到有源区域区域的材料的最外表面下方的各个有源区域的相对端的电介质突起。 有源区域材料在电介质突起上是垂直的。 嵌入式栅极线分别横跨有源区域区域延伸并且在电介质沟槽隔离材料内的紧邻端到端相邻有源区域区域的端部之间延伸。 公开了其他阵列，方法也是如此。

公开(公告)号：US09343462B2

公开(公告)日：2016-05-17

申请号：US14642866

申请日：2015-03-10

Applicant: Micron Technology, Inc.

Inventor： Sanh D. Tang

IPC: H01L21/332 ,  H01L27/102 ,  H01L29/749 ,  H01L29/40 ,  H01L29/66 ,  H01L21/28 ,  H01L21/3205 ,  H01L21/3213 ,  H01L29/423

CPC classification number: H01L27/1027 ,  H01L21/28088 ,  H01L21/32051 ,  H01L21/32055 ,  H01L21/32133 ,  H01L29/401 ,  H01L29/42308 ,  H01L29/66363 ,  H01L29/749

Abstract: Semiconductor devices including a plurality of thyristor-based memory cells, each having a cell size of 4F2, and methods for forming the same are provided. The thyristor-based memory cells each include a thyristor having vertically superposed regions of alternating dopant types, and a control gate. The control gate may be electrically coupled with one or more of the thyristors and may be operably coupled to a voltage source. The thyristor-based memory cells may be formed in an array on a conductive strap, which may function as a cathode or a data line. A system may be formed by integrating the semiconductor devices with one or more memory access devices or conventional logic devices, such as a complementary metal-oxide-semiconductor (CMOS) device.

公开(公告)号：US09337237B2

公开(公告)日：2016-05-10

申请号：US13897615

申请日：2013-05-20

Applicant: Micron Technology, Inc.

Inventor： Sanh D. Tang ,  John K. Zahurak

IPC: H01L27/24 ,  H01L21/22 ,  H01L27/02 ,  H01L45/00

CPC classification number: H01L27/2409 ,  H01L21/22 ,  H01L27/0207 ,  H01L27/2436 ,  H01L27/249 ,  H01L45/04 ,  H01L45/06 ,  H01L45/1226 ,  H01L45/144 ,  H01L45/146

Abstract: Non-volatile memory devices comprising a memory string including a plurality of vertically superimposed diodes. Each of the diodes may be arranged at different locations along a length of the electrode and may be spaced apart from adjacent diodes by a dielectric material. The electrode may electrically couple the diodes of the memory strings to one another and to another memory device, such as, a MOSFET device. Methods of forming the non-volatile memory devices as well as intermediate structures are also disclosed.

公开(公告)号：US20160104709A1

公开(公告)日：2016-04-14

申请号：US14511371

申请日：2014-10-10

Applicant: Micron Technology, Inc.

Inventor： Srinivas Pulugurtha ,  Sourabh Dhir ,  Rajesh N. Gupta ,  Sanh D. Tang ,  Si-Woo Lee ,  Haitao Liu

IPC: H01L27/108 ,  G11C11/407

CPC classification number: H01L27/10826 ,  G11C7/02 ,  G11C11/407 ,  G11C11/4097 ,  H01L27/10879

Abstract: A method for memory device fabrication includes forming a plurality of continuous fins on a substrate. An insulator material is formed around the fins. The continuous fins are etched into segmented fins to form exposed areas between the segmented fins. An insulator material is formed in the exposed areas wherein the insulator material in the exposed areas is formed higher than the insulator material around the fins. A metal is formed over the fins and the insulator material. The metal formed over the exposed areas is formed to a shallower depth than over the fins.

Abstract translation: 用于存储器件制造的方法包括在衬底上形成多个连续的翅片。 在翅片周围形成绝缘体材料。 将连续的翅片蚀刻成分段的翅片以在分段翅片之间形成暴露的区域。 在暴露区域中形成绝缘体材料，其中暴露区域中的绝缘体材料形成为高于鳍片周围的绝缘体材料。 在翅片和绝缘体材料上形成金属。 形成在暴露区域上的金属形成为比鳍片上方浅的深度。

公开(公告)号：US09281402B2

公开(公告)日：2016-03-08

申请号：US14292443

申请日：2014-05-30

Applicant: Micron Technology, Inc.

Inventor： Sanh D. Tang ,  Gordon Haller

IPC: H01L29/78 ,  H01L21/308 ,  H01L29/66 ,  H01L27/088 ,  H01L29/06

CPC classification number: H01L29/785 ,  H01L21/3086 ,  H01L27/0886 ,  H01L29/0649 ,  H01L29/66795 ,  H01L29/7851

Abstract: There is provided fin methods for fabricating fin structures. More specifically, fin structures are formed in a substrate. The fin structures may include two fins separated by a channel, wherein the fins may be employed as fins of a field effect transistor. The fin structures are formed below the upper surface of the substrate, and may be formed without utilizing a photolithographic mask to etch the fins.

Abstract translation: 提供了用于制造翅片结构的翅片方法。 更具体地，翅片结构形成在基板中。 翅片结构可以包括由通道分开的两个翅片，其中翅片可以用作场效应晶体管的翅片。 翅片结构形成在衬底的上表面下方，并且可以在不利用光刻掩模来形成以蚀刻鳍片的情况下形成。

公开(公告)号：US09214627B2

公开(公告)日：2015-12-15

申请号：US14687738

申请日：2015-04-15

Applicant: Micron Technology, Inc.

Inventor： Scott E. Sills ,  Gurtej S. Sandhu ,  Sanh D. Tang ,  John Smythe

IPC: H01L45/00 ,  H01L27/24

CPC classification number: H01L45/1226 ,  H01L27/2409 ,  H01L27/2427 ,  H01L27/2463 ,  H01L27/2481 ,  H01L45/04 ,  H01L45/085 ,  H01L45/124 ,  H01L45/1266 ,  H01L45/142 ,  H01L45/143 ,  H01L45/144 ,  H01L45/145 ,  H01L45/146 ,  H01L45/148

Abstract: Some embodiments include memory cells. The memory cells may have a first electrode, and a trench-shaped programmable material structure over the first electrode. The trench-shape defines an opening. The programmable material may be configured to reversibly retain a conductive bridge. The memory cell may have an ion source material directly against the programmable material, and may have a second electrode within the opening defined by the trench-shaped programmable material. Some embodiments include arrays of memory cells. The arrays may have first electrically conductive lines, and trench-shaped programmable material structures over the first lines. The trench-shaped structures may define openings within them. Ion source material may be directly against the programmable material, and second electrically conductive lines may be over the ion source material and within the openings defined by the trench-shaped structures.

Abstract translation: 一些实施例包括存储器单元。 存储单元可以具有第一电极和在第一电极上方的沟槽状可编程材料结构。 沟槽形状限定开口。 可编程材料可以被配置为可逆地保持导电桥。 存储单元可以具有直接抵靠可编程材料的离子源材料，并且可以在由沟槽状可编程材料限定的开口内具有第二电极。 一些实施例包括存储器单元阵列。 阵列可以具有第一导电线，以及在第一线上的沟槽状可编程材料结构。 沟槽状结构可以在其内限定开口。 离子源材料可以直接抵靠可编程材料，并且第二导电线可以在离子源材料之上并且在由沟槽状结构限定的开口内。

公开(公告)号：US20150325645A1

公开(公告)日：2015-11-12

申请号：US14803662

申请日：2015-07-20

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Song Guo ,  Yushi Hu ,  Roy Meade ,  Sanh D. Tang ,  Michael P. Violette ,  David H. Wells

IPC: H01L29/06

CPC classification number: H01L29/0649 ,  H01L21/02532 ,  H01L21/02639 ,  H01L21/02647 ,  H01L21/76224 ,  H01L21/76283 ,  H01L21/76286 ,  H01L29/04 ,  H01L29/32

Abstract: Disclosed are methods and resulting structures which provide an opening for epitaxial growth, the opening having an associated projection for reducing the size of the contact area on a substrate at which growth begins. During growth, the epitaxial material grows vertically from the contact area and laterally over the projection. The projection provides a stress relaxation region for the lateral growth to reduce dislocation and stacking faults at the side edges of the grown epitaxial material.

公开(公告)号：US09129983B2

公开(公告)日：2015-09-08

申请号：US14066811

申请日：2013-10-30

Applicant: Micron Technology, Inc.

Inventor： Sanh D. Tang

IPC: H01L21/332 ,  H01L29/66 ,  H01L27/102 ,  H01L27/105 ,  H01L27/11 ,  H01L29/74 ,  H01L29/94 ,  H01L21/8229

CPC classification number: H01L29/66386 ,  H01L21/8229 ,  H01L27/1027 ,  H01L27/105 ,  H01L27/11 ,  H01L29/74 ,  H01L29/94

Abstract: A memory cell includes a thyristor having a plurality of alternately doped, vertically superposed semiconductor regions; a vertically oriented access transistor having an access gate; and a control gate operatively laterally adjacent one of the alternately doped, vertically superposed semiconductor regions. The control gate is spaced laterally of the access gate. Other embodiments are disclosed, including methods of forming memory cells and methods of forming a shared doped semiconductor region of a vertically oriented thyristor and a vertically oriented access transistor.

Abstract translation: 存储单元包括具有多个交替掺杂的垂直叠加的半导体区域的晶闸管; 具有存取栅极的垂直取向的存取晶体管; 以及控制门，其操作地横向地邻近交替掺杂的垂直叠加的半导体区域中的一个。 控制门在接入门侧面隔开。 公开了其它实施例，包括形成存储器单元的方法和形成垂直取向晶闸管和垂直取向的存取晶体管的共用掺杂半导体区域的方法。