公开(公告)号：US08445313B2

公开(公告)日：2013-05-21

申请号：US13546684

申请日：2012-07-11

Applicant: Matthew J. Breitwisch ,  Chieh-Fang Chen ,  Shih-Hung Chen ,  Eric A. Joseph ,  Chung Hon Lam ,  Michael F. Lofaro ,  Hsiang-Lan Lung ,  Alejandro G. Schrott ,  Min Yang

Inventor： Matthew J. Breitwisch ,  Chieh-Fang Chen ,  Shih-Hung Chen ,  Eric A. Joseph ,  Chung Hon Lam ,  Michael F. Lofaro ,  Hsiang-Lan Lung ,  Alejandro G. Schrott ,  Min Yang

IPC: H01L21/00

CPC classification number: H01L45/06 ,  H01L45/144 ,  H01L45/1608 ,  H01L45/1683

Abstract: A method of forming bit line aligned to a phase change material that includes forming a pedestal of a sacrificial material on a portion of a lower electrode and forming at least one dielectric material adjacent to the sacrificial material, wherein the at least one dielectric material has an upper surface substantially coplanar with an upper surface of the pedestal of the sacrificial material. The pedestal of the sacrificial material is removed selective to the at least one dielectric material and the lower electrode to provide an opening to an exposed surface of the lower electrode. A phase change material is formed on the exposed surface of the lower electrode, and the opening is filled with a conductive fill material. A self-aligned etch back process is also provided.

Abstract translation: 一种形成与相变材料对准的位线的方法，包括在下电极的一部分上形成牺牲材料的基座并且形成与所述牺牲材料相邻的至少一个电介质材料，其中所述至少一种电介质材料具有 上表面与牺牲材料的基座的上表面基本共面。 牺牲材料的基座被选择性地移除到至少一个电介质材料和下电极以提供到下电极的暴露表面的开口。 在下电极的暴露表面上形成相变材料，并且用导电填充材料填充开口。 还提供了自对准的回蚀工艺。

公开(公告)号：US20130072013A1

公开(公告)日：2013-03-21

申请号：US13234975

申请日：2011-09-16

Applicant: Shih-Hung Chen ,  Chien-An Chen ,  Ying Xiao ,  Ying Zhang

Inventor： Shih-Hung Chen ,  Chien-An Chen ,  Ying Xiao ,  Ying Zhang

IPC: H01L21/768 ,  C23F1/08 ,  H01L21/3065

CPC classification number: H01L21/31138 ,  H01L21/31116 ,  H01L21/76802

Abstract: An etching method comprises etching an oxide layer with a first dc bias of a plasma chamber, removing a photoresist layer with a second dc bias of the plasma chamber and etching through a liner film with a third dc bias of the plasma chamber. In order to reduce the copper deposition on the wall of the plasma chamber, the third dc bias is set to be less than the first and second dc bias.

Abstract translation: 蚀刻方法包括用等离子体室的第一直流偏压蚀刻氧化物层，用等离子体室的第二直流偏压去除光致抗蚀剂层，并通过具有等离子体室的第三直流偏压的衬垫膜进行蚀刻。 为了减少等离子体室壁上的铜沉积，将第三直流偏压设定为小于第一和第二直流偏压。

公开(公告)号：US08304911B2

公开(公告)日：2012-11-06

申请号：US13024546

申请日：2011-02-10

Applicant: Shih-Hung Chen ,  Hang-Ting Lue ,  Yi-Hsuan Hsiao

Inventor： Shih-Hung Chen ,  Hang-Ting Lue ,  Yi-Hsuan Hsiao

IPC: H01L23/48

CPC classification number: H01L27/11582 ,  H01L27/11578

Abstract: A semiconductor structure and a manufacturing method of the same are provided. The semiconductor structure includes a substrate, a first stacked structure, a second stacked structure, a dielectric element, and a conductive line. The first stacked structure and the second stacked structure are disposed on the substrate. Each of the first stacked structure and the second stacked structure includes conductive strips and insulating strips stacked alternately. The conductive strips are separated from each other by the insulating strips. The dielectric element is disposed on the first stacked structure and the second stacked structure and includes a second dielectric portion. The first stacked structure and the second stacked structure are separated from each other by only the second dielectric portion. The conductive line is disposed on the stack sidewalls of the first stacked structure and the second stacked structure far from the second dielectric portion.

Abstract translation: 提供了一种半导体结构及其制造方法。 半导体结构包括基板，第一堆叠结构，第二堆叠结构，电介质元件和导线。 第一堆叠结构和第二堆叠结构设置在基板上。 第一堆叠结构和第二堆叠结构中的每一个包括交替堆叠的导电条和绝缘条。 导电条通过绝缘条彼此分离。 电介质元件设置在第一堆叠结构和第二堆叠结构上并且包括第二电介质部分。 第一堆叠结构和第二堆叠结构仅通过第二电介质部分彼此分离。 导电线设置在第一堆叠结构的堆叠侧壁和远离第二电介质部分的第二堆叠结构中。

公开(公告)号：US08293600B2

公开(公告)日：2012-10-23

申请号：US13311637

申请日：2011-12-06

Applicant: Shih-Hung Chen

Inventor： Shih-Hung Chen

IPC: H01L21/8236

CPC classification number: G11C11/5678 ,  G11C13/0004 ,  G11C2213/52 ,  G11C2213/79 ,  H01L45/06 ,  H01L45/1233 ,  H01L45/1253 ,  H01L45/128 ,  H01L45/143 ,  H01L45/144 ,  H01L45/148 ,  H01L45/16

Abstract: Memory devices and methods for manufacturing are described herein. A memory device as described herein includes a first electrode layer, a second electrode layer, and a thermal isolation structure including a layer of thermal isolation material between the first and second electrode layers. The first and second electrode layers and the thermal isolation structure define a multi-layer stack having a sidewall. A sidewall conductor layer including a sidewall conductor material is on the sidewall of the multi-layer stack. The sidewall conductor material has an electrical conductivity greater than that of the thermal isolation material. A memory element including memory material is on and in contact with the second electrode layer.

Abstract translation: 本文描述了存储器件和制造方法。 如本文所述的存储器件包括第一电极层，第二电极层和包括在第一和第二电极层之间的热隔离材料层的热隔离结构。 第一和第二电极层和热隔离结构限定具有侧壁的多层堆叠。 包括侧壁导体材料的侧壁导体层位于多层叠层的侧壁上。 侧壁导体材料的导电率大于热隔离材料的导电性。 包括存储材料的存储元件在第二电极层上并与其接触。

公开(公告)号：US08243494B2

公开(公告)日：2012-08-14

申请号：US12235773

申请日：2008-09-23

Applicant: Erh-Kun Lai ,  ChiaHua Ho ,  Kuang Yeu Hsieh ,  Shih-Hung Chen

Inventor： Erh-Kun Lai ,  ChiaHua Ho ,  Kuang Yeu Hsieh ,  Shih-Hung Chen

IPC: G11C16/02 ,  H01L29/417

CPC classification number: H01L45/06 ,  G11C11/5678 ,  G11C13/0004 ,  H01L27/2436 ,  H01L45/1233 ,  H01L45/1246 ,  H01L45/144 ,  H01L45/148 ,  H01L45/1666

Abstract: A process in the manufacturing of a resistor random access memory with a confined melting area for switching a phase change in the programmable resistive memory. The process initially formed a pillar comprising a substrate body, a first conductive material overlying the substrate body, a programmable resistive memory material overlying the first conductive material, a high selective material overlying the programmable resistive memory material, and a silicon nitride material overlying the high selective material. The high selective material in the pillar is isotropically etched on both sides of the high selective material to create a void on each side of the high selective material with a reduced length. A programmable resistive memory material is deposited in a confined area previously occupied by the reduced length of the poly, and the programmable resistive memory material is deposited into an area previously occupied by the silicon nitride material.

Abstract translation: 制造具有用于切换可编程电阻存储器中的相位变化的限定熔化区域的电阻器随机存取存储器的过程。 该工艺最初形成了一个支柱，该支柱包括衬底主体，覆盖衬底主体的第一导电材料，覆盖第一导电材料的可编程电阻性存储器材料，覆盖在可编程电阻性存储器材料上的高选择性材料， 选择性材料。 柱中的高选择性材料在高选择性材料的两侧进行各向同性蚀刻，以在长度较小的高选择性材料的每侧产生空隙。 可编程电阻式存储器材料沉积在先前由多晶硅长度减小的限制区域中，并且可编程电阻式存储器材料沉积到先前由氮化硅材料占据的区域中。

公开(公告)号：US20120202333A1

公开(公告)日：2012-08-09

申请号：US13020051

申请日：2011-02-03

Applicant: Matthew J. Breitwisch ,  Chieh-Fang Chen ,  Shih-Hung Chen ,  Eric A. Joseph ,  Chung Hon Lam ,  Michael F. Lofaro ,  Hsiang-Lan Lung ,  Alejandro G. Schrott ,  Min Yang

Inventor： Matthew J. Breitwisch ,  Chieh-Fang Chen ,  Shih-Hung Chen ,  Eric A. Joseph ,  Chung Hon Lam ,  Michael F. Lofaro ,  Hsiang-Lan Lung ,  Alejandro G. Schrott ,  Min Yang

IPC: H01L21/02

CPC classification number: H01L45/06 ,  H01L45/144 ,  H01L45/1608 ,  H01L45/1683

Abstract: A method of forming bit line aligned to a phase change material that includes forming a pedestal of a sacrificial material on a portion of a lower electrode and fowling at least one dielectric material adjacent to the sacrificial material, wherein the at least one dielectric material has an upper surface substantially coplanar with an upper surface of the pedestal of the sacrificial material. The pedestal of the sacrificial material is removed selective to the at least one dielectric material and the lower electrode to provide an opening to an exposed surface of the lower electrode. A phase change material is formed on the exposed surface of the lower electrode, and the opening is filled with a conductive fill material. A self-aligned etch back process is also provided.

Abstract translation: 一种形成与相变材料对准的位线的方法，其包括在下电极的一部分上形成牺牲材料的基座并且与邻近所述牺牲材料的至少一个电介质材料相连，其中所述至少一种电介质材料具有 上表面与牺牲材料的基座的上表面基本共面。 牺牲材料的基座被选择性地移除到至少一个电介质材料和下电极以提供到下电极的暴露表面的开口。 在下电极的暴露表面上形成相变材料，并且用导电填充材料填充开口。 还提供了自对准的回蚀工艺。

公开(公告)号：US20120185753A1

公开(公告)日：2012-07-19

申请号：US13052762

申请日：2011-03-21

Applicant: Shih-Hung Chen ,  Hang-Ting Lue ,  I-Jen Huang

Inventor： Shih-Hung Chen ,  Hang-Ting Lue ,  I-Jen Huang

IPC: G06F11/10

CPC classification number: H01L27/0688 ,  G06F11/1044 ,  G06F11/1048 ,  G06F11/1068 ,  G06F11/1072 ,  G06F11/1076 ,  H01L27/11573 ,  H01L27/11578

Abstract: A structure of 3D memory comprises a plurality of stacking layers and a plurality of cells. The stacking layers are arranged in a three-dimensional array and disposed parallel to each other on a substrate, and the stacking layers comprises a plurality of stacking memory layers. The cells comprises a first group of cells (such as m of cells) for storing information data and a second group of cells (such as n of cells) for storing ECC (error checking and correcting) spare bits. All of the first group and the second group of cells are read out at the same time for performing an ECC function. The ECC spare bits in the 3D memory according to the present disclosure can be constructed at the same physical layer or at the different physical layers. The embodiments can be implemented, but not limited, by a vertical-gate (VG) structure or a finger VG structure.

Abstract translation: 3D存储器的结构包括多个堆叠层和多个单元。 堆叠层被布置成三维阵列并且在基板上彼此平行地布置，并且堆叠层包括多个堆叠存储层。 这些单元包括用于存储信息数据的第一组单元（例如，单元格m）和用于存储ECC（错误检查和校正）备用位的第二组单元（例如n个单元）。 同时读出所有第一组和第二组单元，以执行ECC功能。 根据本公开的3D存储器中的ECC备用位可以在相同的物理层或不同的物理层构造。 实施例可以通过垂直门（VG）结构或手指VG结构来实现但不限于此。

公开(公告)号：US08084842B2

公开(公告)日：2011-12-27

申请号：US12054861

申请日：2008-03-25

Applicant: Shih-Hung Chen

Inventor： Shih-Hung Chen

IPC: H01L29/00

CPC classification number: G11C11/5678 ,  G11C13/0004 ,  G11C2213/52 ,  G11C2213/79 ,  H01L45/06 ,  H01L45/1233 ,  H01L45/1253 ,  H01L45/128 ,  H01L45/143 ,  H01L45/144 ,  H01L45/148 ,  H01L45/16

Abstract: Memory devices and methods for manufacturing are described herein. A memory device as described herein includes a first electrode layer, a second electrode layer, and a thermal isolation structure including a layer of thermal isolation material between the first and second electrode layers. The first and second electrode layers and the thermal isolation structure define a multi-layer stack having a sidewall. A sidewall conductor layer including a sidewall conductor material is on the sidewall of the multi-layer stack. The sidewall conductor material has an electrical conductivity greater than that of the thermal isolation material. A memory element including memory material is on the second electrode layer.

Abstract translation: 本文描述了存储器件和制造方法。 如本文所述的存储器件包括第一电极层，第二电极层和包括在第一和第二电极层之间的热隔离材料层的热隔离结构。 第一和第二电极层和热隔离结构限定具有侧壁的多层堆叠。 包括侧壁导体材料的侧壁导体层位于多层叠层的侧壁上。 侧壁导体材料的导电率大于热隔离材料的导电性。 包括存储材料的存储元件在第二电极层上。

公开(公告)号：US07929340B2

公开(公告)日：2011-04-19

申请号：US12703478

申请日：2010-02-10

Applicant: Hsiang-Lan Lung ,  Rich Liu ,  Shih-Hung Chen ,  Yi-Chou Chen

Inventor： Hsiang-Lan Lung ,  Rich Liu ,  Shih-Hung Chen ,  Yi-Chou Chen

IPC: G11C11/00

CPC classification number: G11C8/10 ,  G11C8/08 ,  G11C13/0004 ,  G11C13/0028 ,  G11C2213/53 ,  G11C2213/79 ,  H01L27/2436 ,  H01L27/2463 ,  H01L45/06 ,  H01L45/1226 ,  H01L45/1233 ,  H01L45/143 ,  H01L45/144 ,  H01L45/148 ,  H01L45/1625 ,  H01L45/165 ,  H01L45/1675

Abstract: A phase change memory cell includes first and second electrodes electrically coupled by a phase change element. At least a section of the phase change element comprises a higher reset transition temperature portion and a lower reset transition temperature portion. The lower reset transition temperature portion comprises a phase change region which can be transitioned, by the passage of electrical current therethrough, from generally crystalline to generally amorphous states at a lower temperature than the higher reset transition temperature portion. The phase change element may comprise an outer, generally tubular, higher reset transition temperature portion surrounding an inner, lower reset transition temperature portion.

Abstract translation: 相变存储单元包括由相变元件电耦合的第一和第二电极。 相变元件的至少一部分包括较高的复位转变温度部分和较低的复位转变温度部分。 下复位转变温度部分包括可以通过电流通过从相对于较高复位转变温度部分的较低温度的大致结晶到大致非晶状态的相变区域。 相变元件可以包括围绕内部，下部复位转变温度部分的外部，大体上管状的较高复位转变温度部分。

公开(公告)号：US07848068B2

公开(公告)日：2010-12-07

申请号：US11740904

申请日：2007-04-26

Applicant: Shih-Hung Chen ,  Ming-Dou Ker

Inventor： Shih-Hung Chen ,  Ming-Dou Ker

IPC: H02H9/00

CPC classification number: H01L27/0266

Abstract: A circuit capable of providing electrostatic discharge (ESD) protection includes a first transistor including a first gate and a first source, the first gate being connected to a conductive pad, an impedance device between the first source and a first power rail capable of providing a resistor, a second transistor including a second gate and a second source, the second source being connected to the first power rail through the impedance device, and a clamp device between the first power rail and a second power rail, wherein the clamp device is capable of conducting a first portion of an ESD current and the second transistor is capable of conducting a second portion of the ESD current as the conductive pad is relatively grounded.

Abstract translation: 能够提供静电放电（ESD）保护的电路包括：第一晶体管，包括第一栅极和第一源极，第一栅极连接到导电焊盘，第一源极与能够提供 电阻器，包括第二栅极和第二源极的第二晶体管，所述第二源极通过所述阻抗器件连接到所述第一电力轨道，以及在所述第一电力轨道和第二电力轨道之间的夹紧装置，其中所述夹紧装置能够 导电ESD电流的第一部分，并且当导电焊盘相对接地时，第二晶体管能够导通ESD电流的第二部分。